;> MemTestSrc
 ^ 0
WRITEC # 1
WRITES # 1
WRITE0 # 1
NEWLINE # 1
READC # 1
CLI # 1
BYTE # 1
WORD # 1
FILE # 1
ARGS # 1
BGET # 1
BPUT # 1
MULTIPLE # 1
OPEN # 1
READLINE # 1
CONTROL # 1
GETENV # 1
EXIT # 1
WRITEI * 256
R0 RN 0
R1 RN 1
R2 RN 2
R3 RN 3
R4 RN 4
R5 RN 5
R6 RN 6
R7 RN 7
R8 RN 8
R9 RN 9
R10 RN 10
R11 RN 11
R12 RN 12
R13 RN 13
R14 RN 14
PC RN 15
 LEADR &1000
 SWI WRITES
 = "Memory tester for ARM 2nd processor",10,13,"Testing up to address &",0
 SWI GETENV
 ADD R12,R1,#20*1024
 TST R12,#20*1024
 MOVNE R12,R1
; MOV R12,#2048*1024
 MOV R10,R12
 BL WORDHX
 SWI WRITES
 = 10,13,"Phase one: incrementing pattern",0
 MOV R7,#4
 MOV R8,#0
PHASE1 LDR R0,P1PTN
 LDR R1,P1INC
 BL ENDADR
PH1FILL STR R0,[R4],#4
 ADD R0,R0,R1
 TEQ R4,R12
 BNE PH1FILL
 SWI WRITEI+"."
 BL ENDADR
 LDR R0,P1PTN
PH1CHK LDR R2,[R4],#4
 TEQ R2,R0
 BNE PH1FAIL
PH1CONT ADD R0,R0,R1
 TEQ R4,R12
 BNE PH1CHK
 STR R0,P1PTN
 SUBS R7,R7,#1
 BNE PHASE1
 TEQ R8,#0
 BNE PHASEDEAD
 SWI WRITES
 = 10,13,"Phase two: TRUE hierarchy",0
 MOV R0,#0
 MVN R1,#0
 MOV R2,#2
PHASE2 BL ENDADR
PHASE2A TST R4,R2
 STREQ R0,[R4],#4
 STRNE R1,[R4],#4
 CMP R4,R12
 BCC PHASE2A
 SWI WRITEI+"."
 BL ENDADR
PHASE2B TST R4,R2
 LDR R3,[R4],#4
 BNE PHASE2B1
PHASE2B2 CMP R0,R3
 BNE PH2FAIL
 B PH2CONT
PHASE2B1 CMP R1,R3
 BNE PH2FAIL
PH2CONT CMP R4,R12
 BCC PHASE2B
 CMP R2,R12
 ADDCC R2,R2,R2
 BCC PHASE2
 TEQ R1,#0
 BEQ PHASE4
 SWI WRITES
 = 10,13,"Phase three: FALSE hierarchy",0
 MVN R0,#0
 MOV R1,#0
 MOV R2,#2
 B PHASE2
PHASE4 TEQ R8,#0
 BNE PHASEDEAD
 SWI WRITES
 = 10,13,"Phase four: Cycling bits",0
 MOV R7,#1
PHASE4A BL ENDADR
 MOV R2,R7
PHASE4A1 STR R2,[R4],#4
 MOV R2,R2,ROR #31
 CMP R4,R12
 BCC PHASE4A1
 SWI WRITEI+"."
 BL ENDADR
 MOV R2,R7
PHASE4B1 LDR R1,[R4],#4
 CMP R1,R2
 BNE PH4FAIL
PH4CONT MOV R2,R2,ROR #31
 CMP R4,R12
 BCC PHASE4B1
 ADDS R7,R7,R7
 BCC PHASE4A
 SWI WRITES
 = 10,13,"All seems OK......",10,13,0
 SWI EXIT
PHASEDEAD SWI WRITES
 = 10,13,"There were &",0
 MOV R10,R8
 BL WORDHX
 SWI WRITES
 = " failures in total",10,13,0
 SWI EXIT
PH1FAIL CMP R8,#10
 ADD R8,R8,#1
 BCS PH1CONT
 SWI WRITES
 = 10,13,"Phase 1 fail at &",0
 MOV R5,R0
 SUB R10,R4,#4
 BL WORDHX
 SWI WRITES
 = " with &",0
 MOV R10,R2
 BL WORDHX
 SWI WRITES
 = " instead of &",0
 MOV R10,R5
 BL WORDHX
 MOV R0,R5
 B PH1CONT
PH2FAIL CMP R8,#10
 ADD R8,R8,#1
 BCS PH2CONT
 SWI WRITES
 = 10,13,"Phase 2 fail at &",0
 SUB R10,R4,#4
 MOV R5,R0
 BL WORDHX
 SWI WRITES
 = " with &",0
 MOV R10,R3
 BL WORDHX
 SWI WRITES
 = " instead of &",0
 TST R4,R2
 MOVNE R10,R1
 MOVEQ R10,R5
 BL WORDHX
 MOV R0,R5
 B PH2CONT
PH4FAIL CMP R8,#10
 ADD R8,R8,#1
 BCS PH4CONT
 SWI WRITES
 = 10,13,"Phase 4 fail at &",0
 SUB R10,R4,#4
 BL WORDHX
 SWI WRITES
 = " with &",0
 MOV R10,R1
 BL WORDHX
 SWI WRITES
 = " instead of &",0
 MOV R10,R2
 BL WORDHX
 B PH4CONT
P1PTN & &86427531
P1INC & &0F020501
WORDSP SWI WRITEI+" "
;print R10 using R0,R6,r9
WORDHX MOV R6,#32-4
WORDLP MOV R0,R10,LSR R6
 AND R0,R0,#15
 CMP R0,#9
 ORRLS R0,R0,#"0"
 ADDHI R0,R0,#"A"-10
 SWI WRITEC
 SUBS R6,R6,#4
 BPL WORDLP
 MOV PC,R14
ENDADR ADR R4,ZEEND
 MOV PC,R14
ZEEND
 END