MODULE Vdd;
FROM KerInOut   IMPORT CELLSET, EmptyCellSet, AddToCellSet, DisposeCellSet,
                       LoadCell, LoadGuts, HaveGuts, SaveCells, ScanHeap,
                       ALL, SDL, OutputText;
FROM KerTypes   IMPORT CELL,PORT,INST,NET,TRANSFM,DIRN,IOTYPE,NETTYPE,LAYER;
FROM KerBuild   IMPORT FindPort;
FROM KerQuery   IMPORT AskIOAndNet;
IMPORT GEN;
FROM MLAP       IMPORT inst, cell, f1, endcell, findcell, fullport, port,
                       connect, net, wire, netf1, portf1, instf1, sepp,
                       sep;
IMPORT MLAP;
FROM CMOS IMPORT poly, metal, pwell, any;
VAR MMCell, ChanCell :CELL;
    ChanEtc :CELLSET;
    MM :INST;
    MML, MMR, MMS, InPort, OutPort, VssL, VssR, VddL, VddR :PORT;
    MMNet, VssNet, VddNet :NET;
    IO :IOTYPE;
BEGIN
   MLAP.debug := TRUE;
   ChanEtc := EmptyCellSet();
   MMCell := findcell ("MM");
   cell ("Vdd");
   MM := inst ("MM", MMCell, r0);
   MML := FindPort (MMCell, "W ");
   MMR := FindPort (MMCell, "E ");
   MMS := FindPort (MMCell, "S ");
   AskIOAndNet (MMS, IO, MMNet);
   VddNet := net("Vdd", any);
   VssNet := net("Vss", any);
   connect (MM, MMNet, Vdd);
   InPort := port ("VddIn", South, metal, On, VddNet);
   VssL := port ("VssL", West, metal, On, VssNet);
   VssR := port ("VssR", East, metal, On, VssNet);
   VddL := port ("VddL", West, metal, On, VddNet);
   VddR := port ("VddR", East, metal, On, VddNet);
   wire (NIL, InPort, 400, MM, MMS);
   wire (NIL, VddL, 800, MM, MML);
   wire (NIL, VddR, 800, MM, MMR);
   wire (NIL, VssL, 0, NIL, VssR);
   wire (NIL, VddL, 0, NIL, VddR);
   sepp (VssR, North, 1200, VddR);
   endcell ();
   ChanCell := findcell ("Vdd");
   AddToCellSet (ChanEtc, ChanCell);
   SaveCells ("Vdd", ChanEtc);
   DisposeCellSet (ChanEtc);
   
END VddVss.