Nov  9 09:30 1984  CHIP6809.toal Page 1


heap CHIP6809
export CHIP6809

from MIDSLICE import MIDSLICE
from LHSPADS import LHSPADS
from RHSPADS import RHSPADS

cell LeftHandSide (cells LHSPADS, MIDSLICE)
   join (LHSPADS <east> MIDSLICE)
endcell LeftHandSide

cell CHIP6809 (cells LeftHandSide, RHSPADS)
   join (LeftHandSide <east> RHSPADS)
endcell CHIP6809

endheap CHIP6809















































Nov  9 09:22 1984  MIDSLICE.toal Page 1


heap MIDSLICE

from Centre import Centre
from TOPPADS import TOPPADS
from chanPPx8 import chanPPx8

export MIDSLICE

cell toproute (cells TOPPADS, chanPPx8)   {*** signals should be
                                               switched over ***}
   join (TOPPADS <south> chanPPx8 rotatedby (2))
endcell toproute

cell MIDSLICE (cells Centre, toproute)
   join (toproute <south> Centre)
endcell MIDSLICE

endheap MIDSLICE













































Nov  9 08:44 1984  Centre.toal Page 1


heap Centre

from totalchipfix import totalchip'
from inputx8 import inputx8
from chanPPx8 import chanPPx8

export Centre

cell botroute (cells inputx8, chanPPx8)
   join (chanPPx8 <south> inputx8)
endcell botroute

cell Centre (cells totalchip', botroute)
   join (totalchip' <south> botroute)
endcell Centre

endheap Centre














































Nov  9 09:16 1984  TOPPADS.toal Page 1


heap TOPPADS
export TOPPADS
from VSS import VSS
from INPAD import INPAD
from OUTPAD import OUTPAD

cell TwTr(cells OUTPAD => Tw, OUTPAD => Tr)
   ports (Tw.Data => TwPad, Tr.Data => TrPad)
   nets  (Tw.Data => TwPad, Tr.Data => TrPad)
   join (Tw rotatedby (2) <east> Tr rotatedby (2))
endcell TwTr

cell TcsROM(cells OUTPAD => Tcs, OUTPAD => ROM)
   ports (Tcs.Data => TcsPad, ROM.Data => ROMPad)
   nets  (Tcs.Data => TcsPad, ROM.Data => ROMPad)
   join (Tcs rotatedby (2) <east> ROM rotatedby (2))
endcell TcsROM

cell RasCas(cells OUTPAD => Ras, OUTPAD => Cas)
   ports (Ras.Data => RasPad, Cas.Data => CasPad)
   nets  (Ras.Data => RasPad, Cas.Data => CasPad)
   join (Ras rotatedby (2) <east> Cas rotatedby (2))
endcell TcsROM

cell ResetQclk(cells INPAD => Reset, INPAD => Qclk)
   ports (Reset.Data => ResetPad, Qclk.Data => QclkPad)
   nets (Reset.Data => ResetPad, Qclk.Data => QclkPad)
   join (Reset rotatedby (2) <east> Qclk rotatedby (2))
endcell TcsROM

cell TwTrTcsROM (cells TwTr, TcsROM)
   join (TwTr <east> TcsROM)
endcell TwTrTcsROM

cell TwTrTcsROMVSS (cells TwTrTcsROM, VSS)
   join (TwTrTcsROM <east> VSS rotatedby (2))
endcell TwTrTcsROMVSS

cell RasCasResetQclk (cells RasCas, ResetQclk)
   join (RasCas <east> ResetQclk)
endcell RasCasResetQclk

cell TOPPADS (cells TwTrTcsROMVSS, RasCasResetQclk)
   join (TwTrTcsROMVSS <east> RasCasResetQclk)
endcell TOPPADS

endheap TOPPADS
















Nov  9 09:28 1984  RHSPADS.toal Page 1


heap RHSPADS

from outputx8 import outputx8
from inputx8 import inputx2
from CORNER import CORNER
from chanPMx8 import chanPMx8 { may need neg-len wires }
{ ******** can we use a chanMPx10 here???? ********** }
export RHSPADS
{****** need a VDD west-goin cell between two pads. ******}
{****** Only trouble is - which two ???             ******}
cell in2out8 (cells inputx2, outputx8)
   ports (inputx2.Data0 => RWin, inputx2.Data1 => Eclk)
   nets  (inputx2.Data0 => RWin, inputx2.Data1 => Eclk)
   join (inputx2 rotatedby (1) <south> outputx8)
endcell in2out8

cell RHSPADS (cells in2out8, CORNER)
   join (in2out8 <south> CORNER rotatedby (1))
endcell RHSPADS

endheap RHSPADS










































Nov  9 06:53 1984  inputx8.toal Page 1


heap inputx8

from INPAD import INPAD
export inputx2, inputx8

{ TTLin generated by MLAP from all file /mnt/graham/all/inpads.all }

cell inputx2 (cells INPAD => inputa, INPAD => inputb)
   ports (inputa.Data => Data0,
          inputb.Data => Data1)
   nets  (inputa.Data => Data0,
          inputb.Data => Data1)
   join (inputa <east> inputb)
endcell inputx2

cell inputx4 (cells inputx2 => inputa, inputx2 => inputb)
   ports (inputb.Data0 => Data2,
          inputb.Data1 => Data3)
   nets  (inputb.Data0 => Data2,
          inputb.Data1 => Data3)
   join (inputa <east> inputb)
endcell inputx4

cell inputx8 (cells inputx4 => inputa, inputx4 => inputb)
   ports (inputb.Data0 => Data4,
          inputb.Data1 => Data5,
          inputb.Data2 => Data6,
          inputb.Data3 => Data7)
   nets  (inputb.Data0 => Data4,
          inputb.Data1 => Data5,
          inputb.Data2 => Data6,
          inputb.Data3 => Data7)
   join (inputa <east> inputb)
endcell inputx8

endheap inputx8



























Nov  9 06:50 1984  outputx8.toal Page 1


heap outputx8

from OUTPAD import OUTPAD
export outputx8

{ output generated by MLAP from ALL file /mnt/graham/m6809/all/output.all }

cell outputx2 (cells OUTPAD => outputa, OUTPAD => outputb)
   ports (outputa.Data => Data0,
          outputb.Data => Data1,
          outputb.guardl => guardr,
          outputb.VddW => VddE,
          outputb.VssW => VssE)
   nets  (outputa.Data => Data0,
          outputb.Data => Data1)
   join (outputa <east> outputb mirrored rotatedby (1))
endcell outputx2

cell outputx4 (cells outputx2 => outputa, outputx2 => outputb)
   ports (outputb.Data0 => Data2,
          outputb.Data1 => Data3)
   nets  (outputb.Data0 => Data2,
          outputb.Data1 => Data3)
   join (outputa <east> outputb)
endcell outputx4

cell outputx8 (cells outputx4 => outputa, outputx4 => outputb)
   ports (outputb.Data0 => Data4,
          outputb.Data1 => Data5,
          outputb.Data2 => Data6,
          outputb.Data3 => Data7)
   nets  (outputb.Data0 => Data4,
          outputb.Data1 => Data5,
          outputb.Data2 => Data6,
          outputb.Data3 => Data7)
   join (outputa rotatedby (1) <north> outputb rotatedby (1))
endcell outputx8

endheap outputx8
























Nov  9 04:27 1984  totalchip.toal Page 1


heap totalchip

from megaroute import megaroute
from chipbody  import chipbody

export totalchip

cell totalchip (cells megaroute, chipbody)
   ignore (
      megaroute.RCSin, megaroute.RCSout, {*** Should be removed esewhere ***}
      megaroute.A15in,
      megaroute.A14in,
      megaroute.A13in,
      megaroute.A12in,
      megaroute.A11in,
      megaroute.A10in,
      megaroute.R/Win,
      megaroute.CountIn,
      megaroute.ROMin,
      megaroute.ResetIn,
      megaroute.CASin,
      megaroute.RASin,
      megaroute.TCSin,
      megaroute.TRin,
      megaroute.TWin,
      megaroute.Ein,
      megaroute.Qin,       { all except Vddin }
      megaroute.A15out,
      megaroute.A14out,
      megaroute.A13out,
      megaroute.A12out,
      megaroute.A11out,
      megaroute.A10out,
      megaroute.CountOut,
      megaroute.ROMout,
      megaroute.ResetOut,
      megaroute.CASout,
      megaroute.RASout,
      megaroute.TCSout,
      megaroute.TRout,
      megaroute.TWout,
      megaroute.Qout)       { all except R/W and E }

   join (megaroute <south> chipbody)
endcell totalchip

endheap totalchip
















Nov  9 03:23 1984  megaroute.toal Page 1


heap megaroute
use micron units
from A10 import A10
from A11 import A11
from A12 import A12
from A13 import A13
from A14 import A14
from A15 import A15
from CAS import CAS
from Cnt import Cnt
from Eclk import Eclk
from Qclk import Qclk
from RAS import RAS
from ROM import ROM
from RW import RW
from Reset import Reset
from TCS import TCS
from TR import TR
from TW import TW
export megaroute

cell p1 (cells A10, A11)
   ports (A10.In => A10o, A11.In => A11o)
   join (A10 <east> A11)
endcell p1

cell p2 (cells A12, A13)
   ports (A12.In => A12o, A13.In => A13o)
   join (A12 <east> A13)
endcell p2

cell p3 (cells A14, A15)
   ports (A14.In => A14o, A15.In => A15o)
   join (A14 <east> A15)
endcell p3

cell p4 (cells Eclk, Qclk)
   ports (Eclk.In => Eclkin,
          Qclk.In => Qclkin, Qclk.top => Qclk_Pad)
   join (Eclk <east> Qclk)
endcell p4

cell p5 (cells RW, Cnt)
   ports (RW.In => RWi, Cnt.In => Counti)
   join (RW <east> Cnt)
endcell p5

cell p6 (cells RAS, TW)
   ports (RAS.In => RASi, RAS.top => RAS_Pad, TW.In => TWi, TW.top => TW_Pad)
   join (RAS <east> TW)
endcell p6

cell p7 (cells TR, TCS)
   ports (TR.In => TRi, TR.top => TR_Pad, TCS.In => TCSi, TCS.top => TCS_Pad)
   join (TR <east> TCS)
endcell p7







Nov  9 03:23 1984  megaroute.toal Page 2



cell p8 (cells ROM, CAS)
   ports (ROM.In => ROMi, ROM.top => ROM_Pad,
          CAS.In => CASi, CAS.top => CAS_Pad)
   join (ROM <east> CAS)
endcell p8

cell p9 (cells A10, A11)
   ports (A10.In => A10Pad, A11.In => A11Pad)
   join (A10 <east> A11)
endcell p9

cell p10 (cells A12, A13)
   ports (A12.In => A12Pad, A13.In => A13Pad)
   join (A12 <east> A13)
endcell p10

cell p11 (cells A14, A15)
   ports (A14.In => A14Pad, A15.In => A15Pad)
   join (A14 <east> A15)
endcell p11

cell p12 (cells Cnt, Reset)
   ports (Cnt.In => CntTrigger, Reset.In => CntRst, Reset.top => Reset_Pad)
   join (Cnt <east> Reset)
endcell p12

cell p13 (cells Eclk, ROM)
   ports (Eclk.In => RowCol, ROM.In => RamRefresh)
   ignore (ROM.top)
   join (Eclk <east> ROM)
endcell p13

cell q1 (cells p1, p2)
   join (p1 <east> p2)
endcell q1

cell q2 (cells p3, p4)
   join (p3 <east> p4)
endcell q2

cell q3 (cells p5, p6)
   join (p5 <east> p6)
endcell q3

cell q4 (cells p7, p8)
   join (p7 <east> p8)
endcell q4

cell q5 (cells p9, p10)
   join (p9 <east> p10)
endcell q5

cell q6 (cells p11, p12)
   join (p11 <east> p12)
endcell q6







Nov  9 03:23 1984  megaroute.toal Page 3



cell r1 (cells q1, q2)
   join (q1 <east> q2)
endcell r1

cell r2 (cells q3, q4)
   join (q3 <east> q4)
endcell r2

cell r3 (cells q5, q6)
   join (q5 <east> q6)
endcell r3

cell s1 (cells r1, r2)
   join (r1 <east> r2)
endcell s1

cell s2 (cells r3, p13)
   join (r3 <east> p13)
endcell s2

cell megaroute (cells s1, s2)
   join (s1 <east> s2)
endcell megaroute


endheap megaroute




































Nov  9 01:05 1984  chipbody.toal Page 1


heap chipbody

from bigtop import bigtop
from mainvdd import mainvdd

export chipbody

cell chipbody (cells bigtop, mainvdd)
   ignore (mainvdd.Vddr, mainvdd.Vddr2)
  {************ FIX IN MAINVDD DOWNWARDS LATER !!!!!!! *************}
   join (mainvdd <north> bigtop)
endcell chipbody

endheap chipbody

















































Nov  7 22:39 1984  bigtop.toal Page 1


heap bigtop

from topchan import topchan
from muxcnttop import muxcnttop

export bigtop

cell bigtop (cells topchan, muxcnttop)
   join (topchan <east> muxcnttop)
endcell bigtop

endheap bigtop



















































Nov  7 22:55 1984  muxcnttop.toal Page 1


heap muxcnttop

from VssPP import VssPP
from VssMP import VssMP
from VssT  import VssT

export muxcnttop, muxtop

cell counttop' (cells VssT, VssPP)
   join (VssT <east> VssPP)
endcell counttop'

cell counttop (cells counttop', VssMP)
   ports (VssMP.In => CkIn, VssMP.Out => CkOut)
   nets  (VssMP.Data => Clock)
   join (counttop' <east> VssMP)
endcell counttop

cell muxtop' (cells VssMP, VssT)
   join (VssMP <east> VssT)
endcell muxtop'

cell muxtop (cells muxtop' => A, muxtop' => B)
   ports (A.In => In0, A.Out => Out0,
          B.In => In1, B.Out => Out1,
          A.VssIn => VssIn0, B.VssIn => VssIn1)
   nets  (A.Data => Data0, B.Data => Data1)
   join (A <east> B)
endcell muxtop

cell muxcnttop (cells muxtop, counttop)
   join (counttop <east> muxtop)
endcell muxcnttop

endheap muxcnttop




























Nov  6 21:29 1984  mainvdd.toal Page 1


heap mainvdd

from maincct import maincct
from VddS import VddS
from VddW import VddW

export mainvdd

cell mainvdd(cells maincct, VddS)
   ports (VddS.A0in => A8in,
          VddS.A1in => A9in,
          VddS.A2in => A10in,
          VddS.A3in => A11in,
          VddS.A4in => A12in,
          VddS.A5in => A13in,
          VddS.A6in => A14in,
          VddS.A7in => A15in)
   nets  (VddS.Vdd => VddSouth)
   join (maincct <south 10u> VddS)
endcell mainvdd
{ ************ Move VddW to InPads + chan *************
cell mainvdd (cells mainvdd', VddW)
   ports (VddW.In0 => In8,
          VddW.In1 => In9,
          VddW.In2 => In10,
          VddW.In3 => In11,
          VddW.In4 => In12,
          VddW.In5 => In13,
          VddW.In6 => In14,
          VddW.In7 => In15in)
   nets  (VddW.Vdd => VddWest)
   join (VddW rotatedby (-1) <east 10u> mainvdd')
endcell mainvdd
******************************************************** }
endheap mainvdd




























Nov  6 16:47 1984  maincct.toal Page 1


heap maincct

from countmux import countmux
from muxroute import muxroute
from plahalf import plalhs => lhs
from chanPMx8 import chanPMx8
export maincct

cell junctcntmux (cells countmux, muxroute)
   ports (muxroute.A8 => A8in,
          muxroute.A9 => A9in,
          muxroute.A10 => A10in,
          muxroute.A11 => A11in,
          muxroute.A12 => A12in,
          muxroute.A13 => A13in,
          muxroute.A14 => A14in,
          muxroute.A15 => A15in)
   join (countmux <west 10u> muxroute)
endcell junctcntmux

cell routecntmux (cells junctcntmux => cntmux, chanPMx8 => chan)
   join (chan rotatedby (1) <east 10u> cntmux)
endcell routecntmux

cell maincct (cells routecntmux => rhs, lhs)
   join (lhs <east 10u> rhs)
endcell maincct

endheap maincct


































Nov  7 14:36 1984  countmux.toal Page 1


heap countmux

from countx8 import countx8
from mux3x8 import mux3x8 => mux

export countmux

cell countmux (cells countx8, mux)
   nets  (countx8.Vdd => CountVdd,
          countx8.Vss => CountVss,
          mux.Vdd => MuxVdd,
          mux.Vss => MuxVss)
   join (countx8 <east 10u> mux)
endcell countmux

endheap countmux















































Nov  6 18:15 1984  countx8.toal Page 1


heap countx8

from counter import count, countin
export countx8

cell countin2 (cells countin, count)
   ports (countin.Up1 => A0out,
          countin.Up2 => A8out,
          countin.Out => Refresh0,
          count.Up1 => A1out,
          count.Up2 => A9out,
          count.Out => Refresh1,
          countin.Down1 => A0in,
          countin.Down2 => A8in,
          count.Down1 => A1in,
          count.Down2 => A9in)
   nets  (countin.term1 => term1_0,
          countin.term2 => term2_0,
          countin.out => out_0,
          countin.out' => out'_0,
          count.term1 => term1_1,
          count.term2 => term2_1,
          count.out => out_1,
          count.out' => out'_1)
   ignore (countin.S, count.S)
   join (countin <east> count)
endcell countin2

cell countx2 (cells count => counta, count => countb)
   ports (counta.Up1 => A0out,
          counta.Up2 => A8out,
          counta.Out => Refresh0,
          countb.Up1 => A1out,
          countb.Up2 => A9out,
          countb.Out => Refresh1,
          counta.Down1 => A0in,
          counta.Down2 => A8in,
          countb.Down1 => A1in,
          countb.Down2 => A9in)
   nets  (counta.term1 => term1_0,
          counta.term2 => term2_0,
          counta.out => out_0,
          counta.out' => out'_0,
          countb.term1 => term1_1,
          countb.term2 => term2_1,
          countb.out => out_1,
          countb.out' => out'_1)
   ignore (counta.S, countb.S)
   join (counta <east> countb)
endcell countx2

cell countin4 (cells countin2, countx2)
   ports (countx2.A0in => A2in,
          countx2.A1in => A3in,
          countx2.A8in => A10in,
          countx2.A9in => A11in,







Nov  6 18:15 1984  countx8.toal Page 2


          countx2.Refresh0 => Refresh2,
          countx2.Refresh1 => Refresh3,
          countx2.A0out => A2out,
          countx2.A1out => A3out,
          countx2.A8out => A10out,
          countx2.A9out => A11out,
          countx2.Refresh0 => Refresh2,
          countx2.Refresh1 => Refresh3)
   nets  (countx2.term1_0 => term1_2,
          countx2.term2_0 => term2_2,
          countx2.term1_1 => term1_3,
          countx2.term2_1 => term2_3,
          countx2.out_0 => out_2,
          countx2.out_1 => out_3,
          countx2.out'_0 => out'_2,
          countx2.out'_1 => out'_3)
   join (countin2 <east> countx2)
endcell countin4

cell countx4 (cells countx2 => countx2a, countx2 => countx2b)
   ports (countx2b.A0in => A2in,
          countx2b.A1in => A3in,
          countx2b.A8in => A10in,
          countx2b.A9in => A11in,
          countx2b.Refresh0 => Refresh2,
          countx2b.Refresh1 => Refresh3,
          countx2b.A0out => A2out,
          countx2b.A1out => A3out,
          countx2b.A8out => A10out,
          countx2b.A9out => A11out,
          countx2b.Refresh0 => Refresh2,
          countx2b.Refresh1 => Refresh3)
   nets  (countx2b.term1_0 => term1_2,
          countx2b.term2_0 => term2_2,
          countx2b.term1_1 => term1_3,
          countx2b.term2_1 => term2_3,
          countx2b.out_0 => out_2,
          countx2b.out_1 => out_3,
          countx2b.out'_0 => out'_2,
          countx2b.out'_1 => out'_3)
   join (countx2a <east> countx2b)
endcell countx4

cell countx8 (cells countin4, countx4)
   ports (countx4.A0in => A4in,
          countx4.A1in => A5in,
          countx4.A2in => A6in,
          countx4.A3in => A7in,
          countx4.A8in => A12in,
          countx4.A9in => A13in,
          countx4.A10in => A14in,
          countx4.A11in => A15in,
          countx4.Refresh0 => Refresh4,
          countx4.Refresh1 => Refresh5,
          countx4.Refresh2 => Refresh6,
          countx4.Refresh3 => Refresh7,







Nov  6 18:15 1984  countx8.toal Page 3


          countx4.A0out => A4out,
          countx4.A1out => A5out,
          countx4.A2out => A6out,
          countx4.A3out => A7out,
          countx4.A8out => A12out,
          countx4.A9out => A13out,
          countx4.A10out => A14out,
          countx4.A11out => A15out,
          countx4.Refresh0 => Refresh4,
          countx4.Refresh1 => Refresh5,
          countx4.Refresh2 => Refresh6,
          countx4.Refresh3 => Refresh7)
   nets  (countx4.term1_0 => term1_4,
          countx4.term2_0 => term2_4,
          countx4.term1_1 => term1_5,
          countx4.term2_1 => term2_5,
          countx4.term1_2 => term1_6,
          countx4.term2_2 => term2_6,
          countx4.term1_3 => term1_7,
          countx4.term2_3 => term2_7,
          countx4.out_0 => out_4,
          countx4.out_1 => out_5,
          countx4.out_2 => out_6,
          countx4.out_3 => out_7)
   ignore (countin4.W, countin4.Vddin)
   ignore (countx4.Outmet', countx4.Outdown, countx4.E,
           countx4.Vssout, countx4.Outup, countx4.Resetout',
           countx4.Out')
   join (countin4 rotatedby (3) <south> countx4 rotatedby (3))
endcell countx8

endheap countx8































Nov  6 16:17 1984  plahalf.toal Page 1


heap plahalf

from pla import pla_decode => pla
from UnderPla import UnderPla

export plalhs

cell plalhs (cells pla, UnderPla => left/right)
   nets (pla.vss => PlaVss)
   ignore (pla.n, pla.w, pla.s, pla.e, pla.dummy)
   join (pla mirrored rotatedby (3) |south 40u| left/right)
endcell plalhs

endheap plahalf

















































Nov  8 22:18 1984  mux3x8.toal Page 1


heap mux3x8

from stretchmux import gtmux3, muxinv, muxbuf0
export mux3x8


cell invxxx(cells muxinv, muxbuf0)
   nets (muxbuf0.c' => c1'l)
   ignore (muxinv.S, muxbuf0.S, muxinv.C1l)
   join (muxinv <west> muxbuf0)
endcell invxxx

cell invdriv1 (cells invxxx=>a, invxxx=>b)
   nets (b.c1' => c1'')
   join (a <west> b)
endcell invdriv1

cell invdriv (cells invdriv1=>a, invdriv1=>b)
   ports (b.Vddr => Vddr2,
          b.Vddl => Vddl2,
          b.Vssr => Vssr2,
          b.Vssl => Vssl2,
          b.C' => C'_2,
          b.Control => Control2)
   nets  (b.Vss => Vss2, b.Vdd => Vdd2,
          b.c1'' => c1'_2, b.c1 => c1_2)
   join (a <north> b)
endcell invdriv

cell mux3x2 (cells gtmux3 => mux3a, gtmux3 => mux3b)
   ports (mux3a.Input1 => A0,
          mux3a.Input2 => A8,
          mux3a.Input3 => Refresh0,
          mux3a.Output => Ram0,
          mux3b.Input1 => A1,
          mux3b.Input2 => A9,
          mux3b.Input3 => Refresh1,
          mux3b.Output => Ram1)
   nets  (mux3a.input1 => A0,
          mux3a.input2 => A8,
          mux3a.input3 => Refresh0,
          mux3a.output => Ram0,
          mux3b.input1 => A1,
          mux3b.input2 => A9,
          mux3b.input3 => Refresh1,
          mux3b.output => Ram1)
   join (mux3a rotatedby (1) <south> mux3b rotatedby (1))
endcell mux3x2

cell mux3x4 (cells mux3x2 => mux3x2a, mux3x2 => mux3x2b)
   ports (mux3x2b.A0 => A2,
          mux3x2b.A1 => A3,
          mux3x2b.A8 => A10,
          mux3x2b.A9 => A11,
          mux3x2b.Refresh0 => Refresh2,
          mux3x2b.Refresh1 => Refresh3,







Nov  8 22:18 1984  mux3x8.toal Page 2


          mux3x2b.Ram0 => Ram2,
          mux3x2b.Ram1 => Ram3)
   nets  (mux3x2b.A0 => A2,
          mux3x2b.A1 => A3,
          mux3x2b.A8 => A10,
          mux3x2b.A9 => A11,
          mux3x2b.Refresh0 => Refresh2,
          mux3x2b.Refresh1 => Refresh3,
          mux3x2b.Ram0 => Ram2,
          mux3x2b.Ram1 => Ram3)
   join (mux3x2a <south> mux3x2b)
endcell mux3x4

cell mux3x8' (cells mux3x4 => mux3x4a, mux3x4 => mux3x4b)
   ports (mux3x4b.A0 => A4,
          mux3x4b.A1 => A5,
          mux3x4b.A2 => A6,
          mux3x4b.A3 => A7,
          mux3x4b.A8 => A12,
          mux3x4b.A9 => A13,
          mux3x4b.A10 => A14,
          mux3x4b.A11 => A15,
          mux3x4b.Refresh0 => Refresh4,
          mux3x4b.Refresh1 => Refresh5,
          mux3x4b.Refresh2 => Refresh6,
          mux3x4b.Refresh3 => Refresh7,
          mux3x4b.Ram0 => Ram4,
          mux3x4b.Ram1 => Ram5,
          mux3x4b.Ram2 => Ram6,
          mux3x4b.Ram3 => Ram7)
   nets  (mux3x4b.A0 => A4,
          mux3x4b.A1 => A5,
          mux3x4b.A2 => A6,
          mux3x4b.A3 => A7,
          mux3x4b.A8 => A12,
          mux3x4b.A9 => A13,
          mux3x4b.A10 => A14,
          mux3x4b.A11 => A15,
          mux3x4b.Refresh0 => Refresh4,
          mux3x4b.Refresh1 => Refresh5,
          mux3x4b.Refresh2 => Refresh6,
          mux3x4b.Refresh3 => Refresh7,
          mux3x4b.Ram0 => Ram4,
          mux3x4b.Ram1 => Ram5,
          mux3x4b.Ram2 => Ram6,
          mux3x4b.Ram3 => Ram7)
   ignore (mux3x4b.C1l, mux3x4b.Vssl1, mux3x4b.C1'l,
           mux3x4b.C0l, mux3x4b.Vssl2, mux3x4b.C0'l)
   join (mux3x4a <south> mux3x4b)
endcell mux3x8'

cell invx2 (cells muxinv => inv1, muxinv => inv2)
   ports (inv2.Vddl => Vddl2,
          inv2.Vddr => Vddr2,
          inv2.Vssr => Vssr2,
          inv2.Vssl => Vssl2,







Nov  8 22:18 1984  mux3x8.toal Page 3


          inv2.C1'l => C1'l2,
          inv2.C1l  => C1l2,
          inv2.Control => Control2)
   nets  (inv2.Vss => Vss2, inv2.Vdd => Vdd2,
          inv2.c1 => c1_2, inv2.c1' => c1'_2)
   ignore (inv1.S, inv2.S)
   join (inv1 <south> inv2)
endcell invx2

cell mux3x8 (cells mux3x8', invx2)
   join (invx2 rotatedby (1) <south> mux3x8')
endcell mux3x8
{
cell mux3x8 (cells mux3x8'', invdriv)
   join (invdriv rotatedby (1) <north> mux3x8'')
endcell mux3x8
}
endheap mux3x8