/* EPC Imp to C Translation Release 4 Version Apr 95 */ #include "imptoc.h" /** 09Dec96 p6sched1.inc */ /** Attempt to provide a scheduler for PentiumPRO */ /***/ /** The Pentium PRO does not fit well with this model. We class U0 as the */ /** general pipeline and U1 as the ALU only. Since ALU instructions can */ /** also go down the General pipe we postulate 2 U1 pipes. THis may mean that*/ /** we try to issue 3 Alu instructions together but this is unlikely due */ /** to register pressure. U2 is the Load Unit and U3 is the store Unit. */ /** We assume triple issue as there are 3 instruction decode units. A serious*/ /** defect is that certain ALU ops using instore operands need the Load Unit */ /** before the ALU. This is only partial modelled by setting LOAD ACCESS PENALTY*/ /** and keeping the ALU stall mechanism for Pentium. Basically we are assuming*/ /** the out-of order logic is clever enough to avoid load stalls */ /*******************************************************************************/ /**/ /* ***********************************************/ /* * PENTIUM BASIC BLOCK SCHEDULING INFORMATION **/ /* ***********************************************/ /**/ /* The scheduling info consists of the following fields: */ /**/ /* unit : Identifies the pentium execution unit which processes the */ /* operation. */ /* blockage: Gives the number of clocks before the execution unit */ /* can be issued with another instruction (assuming no data */ /* hazards). */ /* latency : Gives the number of clocks before the result of the instruction*/ /* is available. */ /* There is a primary and a secondary latency field. The primary*/ /* latency is always used unless the instruction results which */ /* are used belong to the alternatively delayed set of */ /* registers. */ /* A negative primary latency may be given. In this case the actual*/ /* instruction latency is considered to be the absolute magnitiude*/ /* of the value but the calculated stall factor for the */ /* instruction is biased. This is used by load instructions */ /* which have a minimum latency which occurs if there is a cache*/ /* hit but also a larger latency which occurs if there is a miss.*/ /* The stall factor bias allows load instructions to be scheduled*/ /* even earlier than that suggested by the minimum latency if that*/ /* will not cause stalls for other instructions. */ /** The lowest opcode for which scheduling information is maintained */ #define MINSCHOP 0 /** The highest opcode for which scheduling information is maintained */ #define MAXSCHOP 250 /** MIPS must always have a delay slot instruction present for control */ /** flow change instructions (even if it is a NOP) */ #define DELAYSLOTMUSTEXIST 0 /** Annullable delay slots are only supported on the R4000 implementation of MIPS*/ #if((Target==MIPS)&&(targetvariant==R4000)) #define ISANNULLABLEUNTAKEN 1 #else #define ISANNULLABLEUNTAKEN 0 #endif; /** MIPS is internally a Harvard architecture so there are no load/store */ /** access penalties */ #define LOADACCESSPENALTY 0 #define STOREACCESSPENALTY 0 /** General architectural information for MIPS */ #define ISSUPERSCALAR 1 #define ISDOUBLEOPCODE 0 #define ISERFREQUIRED 1 #define ISCRFREQUIRED 1 /** Execution unit information for MIPS */ #define MAXUNITNUM 3 #define U0 1 #define U1 2 #define U2 3 #define U3 4 /* FPU - general */ /* integer unit ie ALU only*/ /* Load Unit */ /* Store Unit*/ static const int NumUnits [U3+1] = {0,1,2,1,1}; /**/ /* If the unit has a reservation station one can despatch the instruction */ /* before the sources are free. It will wait without causing a bubble */ /**/ static const int IsExecRS [U3+1] = {0,0,0,0,0}; /**/ /* if the cpu has shadow registers we need not worry about write */ /* after read stallls or write after write stalls. ( This is oversimplified */ /* but the best that can be done with a simple model) */ /**/ #define HasShadowRegs 1 static char * ExecNames [U3+1] = {"U??","U0","U1","U2","U3"}; static const int UnitNumMap [MAXUNITNUM+1] = {U0,U1,U2,U3}; /** Information for alternatively delayed registers (none on MIPS) */ #define ALTDELAYEDGRF (0xFF00) #define ALTDELAYEDERF 0 #define ALTDELAYEDCRF 0 #define ALTDELAYEDDRF 0 /** Registers for which interference should be ignored ($0 on MIPS) */ #define GRFEXEMPT 0 #define ERFEXEMPT 0 #define CRFEXEMPT 0 #define DRFEXEMPT 0 /** Number of beats in processor simulation scoreboard */ #define CPmax 63 /***/ /***/ static const unsigned char SchedTable [(4*((MAXSCHOP-MINSCHOP)+1))-1-(MINSCHOP)+1] = { /* */ /* |-----------------------| |-----------------------| */ /* | instruction mnemonic | | scheduling | */ /* |-----------------------| |-----------------------| */ /* */ /* Unimp = 0; ! SPECIAL Noform*/ U1, 1, 1, 1, /* adc = 1; ! Intops X2form*/ U0, 1, 2, 2, /* add = 2; ! Intops x2form*/ U1, 0, 1, 1, /* and = 3; ! INTOPSu X2form*/ U1, 0, 1, 1, /* bound = 4; ! INTOPSu X2form*/ U0, 8, 8, 8, /* bt = 5; ! INTOPSu X2form*/ U0, 4, 4, 4, /* call = 6; ! JUMPLINK Jform*/ U1, 0, 1, 1, /* callptr = 7; ! JUMPLINK JRform*/ U0, 1, 1, 1, /* cwde = 8; ! INTOPS Noform*/ U0, 3, 4, 4, /* clc = 9; ! SPECREGrw Noform*/ U0, 2, 2, 2, /* cld = 10; ! SPECREGrw Noform*/ U0, 2, 2, 2, /* cmc = 11; ! SPECREGrw Noform*/ U0, 2, 2, 2, /* cmp = 12; ! INTOPS X2form*/ U1, 0, 1, 1, /* cmpsb = 13; ! STROP NOform*/ U0, 5, 5, 5, /* cmpsd = 14; ! STROP Noform*/ U0, 5, 5, 5, /* cmpb = 12; ! INTOPS X2form*/ U1, 0, 1, 1, /* cdq = 16; ! INTOPS NoForm*/ U1, 0, 1, 1, /* dec = 17; ! INTOPS X1form*/ U1, 0, 1, 1, /* div = 18; ! INTOPSu X2iform*/ U0, 41, 42, 42, /* enter = 19; ! StkForm X1lform*/ U0, 15, 15, 15, /* idivide = 20; ! INTOPS X2iform*/ U0, 46, 47, 47, /* imul = 21; ! INTOPS X2iform*/ U0, 1, 4, 4, /* imuld = 22; ! INTOPS X2iform*/ U0, 1, 4, 4, /* inc = 23; ! INTOPS X1form*/ U1, 0, 1, 1, /* JO = 24; ! BCC JForm*/ U1, 0, 1, 1, /* JNO = 25; ! BCC JForm*/ U1, 0, 1, 1, /* JB = 26; ! BCC JForm*/ U1, 0, 1, 1, /* JNB = 27; ! BCC JForm*/ U1, 0, 1, 1, /* JE = 28; ! BCC JForm*/ U1, 0, 1, 1, /* JNE = 29; ! BCC JForm*/ U1, 0, 1, 1, /* JBE = 30; ! BCC JForm*/ U1, 0, 1, 1, 0, 0, 0, 0, /* JA = 32; ! BCC JForm*/ U1, 0, 1, 1, /* JS = 33; ! BCC JForm*/ U1, 0, 1, 1, /* JNS = 34; ! BCC JForm*/ U1, 0, 1, 1, /* JP = 35; ! BCC JForm*/ U1, 0, 1, 1, /* JNP = 36; ! BCC JForm*/ U1, 0, 1, 1, /* JL = 37; ! BCC JForm*/ U1, 0, 1, 1, /* JGE = 38; ! BCC JForm*/ U1, 0, 1, 1, /* JLE = 39; ! BCC JForm*/ U1, 0, 1, 1, /* JG = 40; ! BCC JForm*/ U1, 0, 1, 1, /* jmp = 41; ! BCC Jform*/ U1, 0, 1, 1, /* jmpptr = 42; ! BCC JRform*/ U0, 2, 2, 2, /* LAHF = 43; ! SPECREGrw NoForm*/ U0, 2, 2, 2, /* les = 44; ! INTLOAD X2Form*/ U0, 2, 3, 3, /* lds = 45; ! INTLOAD X2Form*/ U0, 2, 3, 3, /* lea = 46; ! INTOPS X2Form*/ U1, 0, 1, 1, /* lbnox = 47; ! INTLOAD X2Form*/ U1, 0, 1, 1, /* lb = 48; ! INTLOAD X2Form*/ U2, 1, 3, 3, /* lbu = 49; ! INTLOAD X2Form*/ U2, 1, 3, 3, /* lh = 50; ! INTLOAD X4Form*/ U2, 1, 3, 3, /* lhu = 51; ! INTLOAD X2Form*/ U2, 1, 3, 3, /* lw = 52; ! INTLOAD X2Form*/ U2, 1, 3, 3, /* leave = 53; ! SPECIAL StkForm*/ U0, 3, 3, 3, /* lodsb = 54; ! STROP Noform*/ U0, 1, 2, 2, /* lodsd = 55; ! STROP NOform*/ U0, 1, 2, 2, /* mov = 56; ! INTOPSu X1form*/ U1, 0, 1, 1, /* movsr = 57; ! SPECREGrw X1form*/ U0, 2, 3, 3, /* movsb = 58; ! STROP Noform*/ U0, 4, 4, 4, /* movsd = 59; ! STROP NOform*/ U0, 4, 4, 4, /* movsx = 60; ! STROP NOform*/ U1, 0, 1, 1, /* movzx = 60; ! STROP X2form*/ U0, 1, 1, 1, /* movb = 62; ! INTOPSu X1form*/ U1, 0, 1, 1, /* mul = 63; ! INTOPSu X2iForm*/ U0, 1, 4, 4, /* neg = 64; ! INTOPS X1form*/ U1, 0, 1, 1, /* nop = 65; ! SPECIAL Noform*/ U1, 0, 1, 1, /* not = 66; ! INTOPSu X1form*/ U0, 0, 1, 1, /* or = 67; ! INTOPSu X2form*/ U1, 0, 1, 1, /* pop = 68; ! SPECIAL Stkform*/ U2, 1, 3, 3, /* push = 69; ! SPECIAL Stkform*/ U3, 1, 1, 1, /* rol = 70; ! SHIFTS SLitform*/ U1, 0, 1, 1, /* rolv = 71; ! SHIFTS X2iForm*/ U0, 0, 1, 1, /* ror = 72; ! SHIFTS Slitform*/ U1, 0, 1, 1, /* rorv = 73; ! SHIFTS X2iForm*/ U0, 0, 1, 1, /* SAHF = 74; ! SPECREGrw NoForm*/ U0, 2, 2, 2, /* sb = 75; ! INTSTORE X2Form*/ U3, 1, 1, 1, /* st = 76; ! INTSTORE X2Form*/ U3, 1, 1, 1, /* sh = 77; ! INTSTORE X2Form*/ U3, 1, 1, 1, /* SETO = 78; ! INTOPSu X1Form*/ U1, 1, 1, 1, 0, 0, 0, 0, /* SETNO = 80; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETB = 81; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETNB = 82; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETE = 83; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETNEQ = 84; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETBE = 85; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETA = 86; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETS = 87; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETNS = 88; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETP = 89; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETNP = 90; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETL = 91; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETGE = 92; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETLEQ = 93; ! INTOPSu X1Form*/ U1, 0, 1, 1, /* SETG = 94; ! INTOPSu X1Form*/ U1, 0, 1, 1, 0, 0, 0, 0, /* sal = 96; ! SHIFTS SLitForm*/ U0, 0, 1, 1, /* salv = 97; ! SHIFTS X2iForm*/ U0, 1, 1, 1, /* shl = 98; ! SHIFTS SLitForm*/ U0, 0, 1, 1, /* shlv = 99; ! SHIFTS X2iForm*/ U0, 1, 1, 1, /* sar =110; ! SHIFTS SLitForm*/ U0, 0, 1, 1, /* sarv =101; ! SHIFTS X2iForm*/ U0, 1, 1, 1, /* shr =112; ! SHIFTS SLitForm*/ U0, 0, 1, 1, /* shrv =103; ! SHIFTS X2iForm*/ U0, 1, 1, 1, /* shld =104; ! SHIFTS SLitForm*/ U0, 1, 1, 1, /* shldv =105; ! SHIFTS ShForm*/ U0, 1, 1, 1, /* shrd =106; ! SHIFTS SLitForm*/ U0, 1, 1, 1, /* shrdv =107; ! SHIFTS ShForm*/ U0, 1, 1, 1, /* sbb =108; ! INTOPS X2form*/ U1, 0, 1, 1, /* sub =109; ! INTOPS X2form*/ U1, 0, 1, 1, /* stc =110; ! SPECREGrw NoForm*/ U0, 2, 2, 2, 0, 0, 0, 0, /* std =112; ! SPECREGrw NoForm*/ U0, 2, 2, 2, /* stosb =113; ! STROP NoForm*/ U0, 3, 3, 3, /* stosw =114; ! STROP NoForm*/ U0, 3, 3, 3, /* testi =115; ! INTOPSu X1lform*/ U1, 0, 1, 1, /* test =116; ! INTOPSu X2Form*/ U1, 0, 1, 1, /* wait =117; ! SPECIAL NOform*/ U0, 1, 1, 1, /* xchg =118; ! INTSTORE X2form*/ U0, 2, 3, 3, /* xor =119; ! INTOPSu X1form*/ U1, 0, 1, 1, /* xori =120; ! INTOPSu X2form*/ U1, 0, 1, 1, /* ret =121; ! SPECIAL NoForm*/ U1, 0, 1, 1, /* popfd =122; ! SPECREGrw NOform*/ U0, 2, 2, 2, /* pushfd =123; ! SPECREGrw NOform*/ U0, 3, 3, 3, /* bswap =124; ! SPECIAL NoForm*/ U1, 0, 1, 1, /* retn =125; ! SPECIAL NoForm*/ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, /* Cmovcc =126-141; ! INTOPSu X2Form */ U1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /* FILD =144; ! FPLOAD F1Form*/ U0, 1, 3, 3, /* FLDd =145; ! FPLOAD F1Form*/ U2, 1, 1, 1, /* FLDm =146; ! FPLOAD F1Form*/ U2, 1, 1, 1, /* FISTP =147; ! FPSTORE F2pForm*/ U0, 1, 4, 4, /* FSTPd =148; ! FPSTORE F2pForm*/ U3, 1, 1, 1, /* FSTPm =149; ! FPSTORE F2pForm*/ U3, 1, 1, 1, /* FIST =150; ! FPSTORE F2Form*/ U0, 1, 4, 4, /* FSTd =151; ! FPSTORE F2Form*/ U3, 1, 1, 1, /* FSTm =152; ! FPSTORE F2Form*/ U3, 1, 1, 1, /* FIADDm =153; ! FPOPS2 FmForm*/ U0, 3, 7, 7, /* FADDd =154; ! FPOPS2 FmForm*/ U0, 1, 4, 3, /* FADDm =155; ! FPOPS2 FmForm*/ U0, 1, 4, 3, /* FADDP =156; ! FPOPS2 F2Form*/ U0, 1, 4, 4, /* FADD =157; ! FPOPS2 F2Form*/ U0, 1, 4, 4, /* FIMULm =158; ! FPOPS2 FmForm*/ U0, 4, 7, 7, 0, 0, 0, 0, /* FMULd =160; ! FPOPS2 FmForm*/ U0, 2, 5, 5, /* FMULm =161; ! FPOPS2 FmForm*/ U0, 2, 5, 5, /* FMULP =162; ! FPOPS2 F2Form*/ U0, 2, 5, 5, /* FMUL =163; ! FPOPS2 F2Form*/ U0, 2, 5, 5, /* FISUBm =164; ! FPOPS2 FmForm*/ U0, 3, 7, 7, /* FSUBd =165; ! FPOPS2 FmForm*/ U0, 1, 4, 4, /* FSUBm =166; ! FPOPS2 FmForm*/ U0, 1, 4, 4, /* FSUBP =167; ! FPOPS2 F2Form*/ U0, 1, 4, 4, /* FSUB =168; ! FPOPS2 F2Form*/ U0, 1, 4, 4, /* FISUBRm =169; ! FPOPS2 FmForm*/ U0, 7, 8, 8, /* FSUBRd =170; ! FPOPS2 FmForm*/ U0, 1, 4, 4, /* FSUBRm =171; ! FPOPS2 FmForm*/ U0, 1, 4, 4, /* FSUBRP =172; ! FPOPS2 F2pForm*/ U0, 1, 4, 4, /* FSUBR =173; ! FPOPS2 F2Form*/ U0, 1, 4, 4, /* FIDIVm =174; ! FPOPS2 FmForm*/ U0, 42, 43, 43, 0, 0, 0, 0, /* FDIVd =176; ! FPOPS2 FmForm*/ U0, 39, 40, 40, /* FDIVm =177; ! FPOPS2 FmForm*/ U0, 39, 40, 40, /* FDIVP =178; ! FPOPS2 F2Form*/ U0, 39, 40, 40, /* FDIV =179; ! FPOPS2 F2Form*/ U0, 39, 40, 40, /* FIDIVRm =180; ! FPOPS2 FmForm*/ U0, 42, 43, 43, /* FDIVRd =181; ! FPOPS2 FmForm*/ U0, 39, 40, 40, /* FDIVRm =182; ! FPOPS2 FmForm*/ U0, 39, 40, 40, /* FDIVRP =183; ! FPOPS2 F2Form*/ U0, 39, 40, 40, /* FDIVR =184; ! FPOPS2 F2Form*/ U0, 39, 40, 40, /* FICOMm =185; ! FPCOMPARE FmForm*/ U0, 4, 8, 8, /* FICOMPm =186; ! FPCOMPARE FmForm*/ U0, 4, 8, 8, /* FCOMd =187; ! FPCOMPARE FmForm*/ U0, 1, 1, 1, /* FCOMm =188; ! FPCOMPARE FmForm*/ U0, 1, 1, 1, /* FCOM =189; ! FPCOMPARE F2Form*/ U0, 1, 1, 1, /* FCOMPd =190; ! FPCOMPARE FmForm*/ U0, 1, 1, 1, 0, 0, 0, 0, /* FCOMPm =192; ! FPCOMPARE FmForm*/ U0, 1, 1, 1, /* FCOMP =193; ! FPCOMPARE F2pForm*/ U0, 1, 1, 1, /* FCOMPP =194; ! FPCOMPARE F2ppForm*/ U0, 1, 1, 1, /* FLDCW =195; ! SPECREGrw X2iForm*/ U0, 1, 2, 2, /* FSTCW =196; ! SPECREGrw X2iForm*/ U0, 2, 2, 2, /* FSTSW =197; ! SPECREGrw X2iForm*/ U0, 2, 2, 2, /* FTST =198; ! FPCOMPARE F1Form*/ U0, 1, 1, 1, /* FCHS =199; ! FPOPS1 F1Form*/ U0, 1, 1, 1, /* FLDZ =200; ! FPOPS1 F1Form*/ U0, 1, 1, 1, /* FLD1 =201; ! FPOPS1 F1Form*/ U0, 1, 2, 2, /* FLDL2E =202; ! FPOPS1 F1Form*/ U0, 1, 4, 4, /* FLDLN2 =203; ! FPOPS1 F1Form*/ U0, 1, 4, 4, /* FLDLG2 =204; ! FPOPS1 F1Form*/ U0, 1, 4, 4, /* FLDPI =205; ! FPOPS1 F1Form*/ U0, 1, 4, 4, /* FABS =206; ! FPOPS1 F1Form*/ U0, 1, 1, 1, 0, 0, 0, 0, /* FDECSTP =208; ! SPECREGrw NoForm*/ U0, 1, 1, 1, /* FRNDINT =209; ! FPOPS1 F1Form*/ U0, 9, 10, 10, /* FXCH =210; ! SPECREGrw NoForm*/ U1, 1, 1, 1, /* FSQRT =211; ! FPOPS1 F1Form*/ U0, 30, 31, 31, /* FSIN =212; ! FPOPS1 F1Form*/ U0, 30, 31, 31, /* FCOS =213; ! FPOPS1 F1Form*/ U0, 30, 31, 31, /* FPTAN =214; ! FPOPS1 F2Form*/ U0, 30, 31, 31, /* FPATAN =215; ! FPOPS2 F2pForm*/ U0, 30, 31, 31, /* F2XM1 =216; ! FPOPS1 F1Form*/ U0, 30, 31, 31, /* FYL2X =217; ! FPOPS2 F2pForm*/ U0, 30, 31, 31, /* FPREM =218; ! FPOPS2 F2Form*/ U0, 16, 17, 17, /* FPREM1 =219; ! FPOPS2 F2Form*/ U0, 16, 17, 17, /* FILDd =220; ! FPLOAD F1Form*/ U0, 3, 4, 4, /* FINIT =221; ! SPECREGrw NoForm*/ U0, 16, 17, 17, /* FINCSTP =222; ! SPECREGrw NoForm*/ U0, 1, 1, 1, 0, 0, 0, 0, /* rFADD =224; ! FPOPS2 F2rForm*/ U0, 1, 4, 4, /* rFSUB =225; ! FPOPS2 F2rForm*/ U0, 1, 4, 4, /* rFSUBR =226; ! FPOPS2 F2rForm*/ U0, 1, 4, 4, /* rFMUL =227; ! FPOPS2 F2rForm*/ U0, 2, 4, 4, /* rFDIV =228; ! FPOPS2 F2rForm*/ U0, 39, 40, 40, /* rFDIVR =229; ! FPOPS2 F2rForm*/ U0, 39, 40, 40, /* rFADDP =230; ! FPOPS2 F2rForm*/ U0, 1, 4, 4, /* rFSUBP =231; ! FPOPS2 F2rForm*/ U0, 1, 4, 4, /* rFSUBRP =232; ! FPOPS2 F2rForm*/ U0, 1, 4, 4, /* rFMULP =233; ! FPOPS2 F2rForm*/ U0, 2, 4, 4, /* rFDIVP =234; ! FPOPS2 F2rForm*/ U0, 39, 40, 40, /* rFDIVRP =235, ! FPOPS2 F2rForm*/ U0, 39, 40, 40, /* FISTdP =236; ! FPSTORE F2pForm*/ U0, 6, 6, 6, /* FLDq =237; ! FPLOAD F1Form*/ U2, 2, 3, 3, /* FSTPq =238; ! FPSTORE F2pForm*/ U3, 2, 3, 3, /* FCMOVcc =239-46; ! FPOPS2 F2Form */ U0, 1, 1, 1, /* FCMOVcc =239-46; ! FPOPS2 F2Form */ U0, 1, 1, 1, /* FCMOVcc =239-46; ! FPOPS2 F2Form */ U0, 1, 1, 1, /* FCMOVcc =239-46; ! FPOPS2 F2Form */ U0, 1, 1, 1, /* FCMOVcc =239-46; ! FPOPS2 F2Form */ U0, 1, 1, 1, /* FCMOVcc =239-46; ! FPOPS2 F2Form */ U0, 1, 1, 1, /* FCMOVcc =239-46; ! FPOPS2 F2Form */ U0, 1, 1, 1, /* FCMOVcc =239-46; ! FPOPS2 F2Form */ U0, 1, 1, 1, /* FCOMI =247; ! FPOPS2 F2Form */ U0, 1, 1, 1, /* FUCOMI =248; ! FPOPS2 F2Form */ U0, 1, 1, 1, /* FCOMIP =249; ! FPOPS2 F2pForm */ U0, 1, 1, 1, /* FUCOMIP =250; ! FPOPS2 F2pForm */ U0, 1, 1, 1}; /***/ /************************** end of p5sched.inc *********************************/ /***/ /* end of automatic translation */