! LANCE/SPEAR data structure definitions

%recordformat df(%half lowad, %byte control,highad,  {rx/tx buffer descriptor
                 %short minus, %half plus)

%recordformat ibf(%half mode,pa0,pa2,pa4,            {Initialisation Block
                  la0,la2,la4,la6,
                  %half lowrad, %byte rcount,highrad,
                  %half lowtad, %byte tcount,hightad)

%recordformat drf(%record(df)%array desc(0:127))     {descriptor ring

{RW read-write
{RO read-only  (any write ignored)
{CO clear-only (write with one clears, with zero ignored)
{SO set-only   (write with one sets, with zero ignored)
{*  indicates LANCE feature not implemented by SPEAR

! CSR0 bits

%consthalf %c
c err  = 16_8000, { RO  babl!cerr!miss!merr
c babl = 16_4000, { RCO packet too long
c cerr = 16_2000, {*RCO collision test error
c miss = 16_1000, { RCO no more rx descriptors
c merr = 16_0800, {*RCO dma timeout
c rint = 16_0400, { RCO r ring entry updated
c tint = 16_0200, { RCO t ring entry updated
c idon = 16_0100, { RCO initialisation completed
c intr = 16_0080, { RO  babl!miss!merr!rint!tint!idon
c inea = 16_0040, { RW  allow INTR to interrupt
c rxon = 16_0020, { RO  receiver is enabled
c txon = 16_0010, { RO  transmitter is enabled
c tdmd = 16_0008, { SO  kick transmitter
c stop = 16_0004, { RSO stops everything
c strt = 16_0002, { RSO starts everything
c init = 16_0001, { RSO initialises everything
c echo = 16_7f40  {sum of clearable and writeable bits

! CSR1 is the low part of the IB address

! CSR2 is the high part of the IB address

! CSR3 bits

%consthalf %c
bswp=4, {* invert data byte sex
acon=2, {* invert sense of ALE pin
bcon=1  {* reconfigure BM1,BM0,HOLD pins

! IB_MODE bits

%consthalf %c
m prom = 16_8000, {* promiscuous mode (not in for now)
m intl = 16_0040, {* internal loopback
m drty = 16_0020, {* disable tx retry on collision
m coll = 16_0010, {* perform collision test
m dtcr = 16_0008, {* disable tx crc generation
m loop = 16_0004, {* loopback mode
m dtx  = 16_0002, {  disable TD ring access
m drx  = 16_0001  {  disable RD ring access

! IB_PA0:4 are the 6 DTE address bytes  {* not in for now

! IB_LA0:6 preload the multicast address filter  {* not in for now

! IB_RCOUNT and TCOUNT determine how many entries there area in
! the receive and transmit descriptor rings, there are 1<<(count>>5).
! IB_HIGHxAD<<16+IB_LOWxAD point to the first entry in each ring.
! The rings must be on an 8-byte boundary.

! Descriptor ring entries

! In both rx and tx descriptors, _HIGHAD<<16+_LOWAD points to the
! data buffer, _CONTROL comprises the flag bits defined below.
! _MINUS is minus the size of the receive buffer or number of
! bytes in a transmit buffer.
! _PLUS is the number of bytes of data in the receive buffer, or, in the
! case of the transmitter {*}, a collection of error bits and a TDR counter.

! desc_CONTROL bits

%constbyte %c
r own  = 16_80, {  entry owned by (0:program,1:device)
r err  = 16_40, {  fram!oflo!crc!buff
r fram = 16_20, {* CRC error and non-multiple of 8 bits
r oflo = 16_10, {* SILO overflow
r crc  = 16_08, {* CRC error
r buff = 16_04, {  no more descriptors
r stp  = 16_02, {  this buffer is first of a packet
r enp  = 16_01  {  this buffer is last of a packet

%consthalf %c
t own  = 16_80, {  entry owned by (0:program,1:device)
t err  = 16_40, {  lcol!lcar!buff!uflo!rtry
t more = 16_10, {* two or more retransmissions were required
t one  = 16_08, {* one retransmission was required
t def  = 16_04, {* transmission was deferred
t stp  = 16_02, {  first buffer of a packet
t enp  = 16_01  {  last buffer of a packet

! tx desc_PLUS bits

%consthalf %c
d buff = 16_8000, {  no more descriptors (implies UFLO)
d uflo = 16_4000, {* SILO underflowed
d lcol = 16_1000, {* late collision
d lcar = 16_0800, {* loss of carrier
d rtry = 16_0400  {* gave up after 16 attempts (1 if DRTY#0)