$ UNIBUS interface for Ethernet board

define land=nor,lor=nand,lnand=or,lnor=and

spec r (i) -> o
spec c (i) -> o
spec pu(vcc)->o
spec comparator (a<7:0>,b<7:0>,e\) -> eq\
spec xcvr (b\<3:0>,i<3:0>,e\) -> b\<3:0>,o<3:0>
spec b16 (i<1:8>) -> o<1:8>   $ Blank socket for switches
spec tsbuf (i,e\) -> o
spec u74 (d,s\,r\,c) -> q,q\
spec u123 (a\,b,c,rc,xc) -> q,q\
spec u124 (range,control,x1,x2,en\) -> out
spec u155 (b,a,c4,c\0,e\4,e\0) -> y\<7:0>
spec u157 (a<1:4>,b<1:4>,sel,en\) -> y<1:4>
spec u175 (in<3:0>,r\,c) -> out<3:0>,out\<3:0>
spec u191 (i<3:0>,up\dn,en\,ld\,c) -> o<3:0>,maxmin,rip\
spec u374 (i<7:0>,c,e\) -> q<7:0>
spec u244 (i<7:0>,e4\,e0\) -> o<7:0>
spec fpla (in<0:15>,ce\) -> out<0:7>

unit ubenet(

 $ IO lines

  ba\<17:0>,
  bc\<1:0>,
  bd\<15:0>,
  bmsyn\,bssyn\,bbbsy\,
 
  ed<7:0>,
 
$ Input lines

  bbgi<7:4>,bnpgi,binit\,
 
  eiowr\,eiord\,edack2\,edack3\,
  ea0,ewlt\,erlr\,erlt\,
 
$ Power lines

  .vcc,.vcc,.vcc,.vcc,.m15,.m15,.m15,.m15,.p15,.p15,.p15,
  .gnd,.gnd,.gnd,.gnd,.gnd,.gnd,.gnd,.gnd,

  .vcc,.vcc,.vcc,.vcc,.gnd,.gnd,.gnd,.gnd,
  .m12,.m12,.p12,.p12,.m5,.m5,
  .tvcc,.tvcc,.tgnd,.tgnd

  ) -> (
 
$ IO lines as above

  ba\<17:0>,bc\<1:0>,bd\<15:0>,bmsyn\,bssyn\,bbbsy\,
  ed<7:0>,
 
$ Output lines

  biv\<8:2>,bintr\,
  bbr\<7:4>,bnpr\,
  bbgo<7:4>,bnpgo,bsack\,
 
  edrq2,edrq3,eint\)
 
  on Deczap4

  pins (
$ Even: 33-(n/2) A,  Odd: 32-((n-1)/2) C
  ed1,ee2,ed2,ek1,ek2,ec1,el1,ep1,er1, $ ba\<17:9>
  en2,ep2,eu1,ev1,eu2,ev2,ef1,eh1,eh2, $ ba\<8:0>
  ef2,ej2,                             $ bc\<1:0>
  cd2,ce2,cf2,ch2,ch1,cj2,ck2,cl2,     $ bd\<15:8>
  cm2,cv2,cp2,cn2,ct2,cu2,cr2,cs2,     $ bd\<7:0>
  ee1,fc1,fd1,                         $ bmsyn\,bssyn\,bbbsy\
  08c,09c,10c,11c,12c,13c,14c,15c,     $ ed<7:0>
  dk2,dm2,dp2,ds2,ca1,dl1,             $ bbgi<7:4>,bnpgi,binit\
  30a,29a,26c,25c,                     $ eiowr\,eiord\,dack2\,dack3\
  22c,21c,19c,18c,                     $ ea0,ewlt\,erlr\,erlt\,
  ca2,da2,ea2,fa2,cb2,db2,eb2,fb2,     $ .vcc,.m15
  dp1,dr1,ds1,                        $ .p15
  cc2,ct1,dc2,dt1,ec2,et1,fc2,ft1,     $ .gnd
  02c,02a,01c,01a,                     $ .vcc
  04c,04a,03c,03a,                     $ .gnd
  07c,07a,05c,05a,                     $ .m12,.m12,.p12,.p12
  06c,06a,                             $ .m5
  31c,31a,32c,32a,                     $ .tvcc,.tvcc,.tgnd,.tgnd
                                       $   ->
  ed1,ee2,ed2,ek1,ek2,ec1,el1,ep1,er1, $ ba\<17:9>
  en2,ep2,eu1,ev1,eu2,ev2,ef1,eh1,eh2, $ ba\<8:0>
  ef2,ej2,                             $ bc\<1:0>
  cd2,ce2,cf2,ch2,ch1,cj2,ck2,cl2,     $ bd\<15:8>
  cm2,cv2,cp2,cn2,ct2,cu2,cr2,cs2,     $ bd\<7:0>
  ee1,ej1,fd1,                         $ bmsyn\,bssyn\,bbbsy\
  08c,09c,10c,11c,12c,13c,14c,15c,     $ ed<7:0>
  fk1,fh1,ff2,ff1,fn2,fl1,fe2,fm1,     $ biv\<8:2>,bintr\
  dd2,de2,df2,dh2,fj1,                 $ bbr\<7:4>,bnpr\
  dl2,dn2,dr2,dt2,cb1,ft2,             $ bbgo<7:4>,bnpgo,bsack\
  24c,23c,17c)                         $ edrq2,edrq3,eint\

unit acq (xatn,gi\,rbbsy,rssyn)
      -> (sack\,master,master\,go\,br)
  inv (gi\) -> gi
  u74 (.L,catn\,.H,xatn) -> ?,atn
  and (atn,sack\) -> br
  u74 (atn,.H,.reset\,gi) -> gt,gt\
  or (gi,.L) -> gi'  or (gi',gi') -> gi''
  nand (gi'',gt\) -> go\
  nor (master,.reset) -> catn\
  u74 (gt,.H,atn,gi'') -> sack,sack\
  nand (rssyn,master) -> cm\  lnor (cm\,.reset\) -> cmaster\
  land (gi,rbbsy,rssyn) -> free
  u74 (sack,.H,cmaster\,free) -> master,master\
end

unit transmitter (ea0,erlr\,edack2\,eiord\,
         wc\,wdbrh\,wdbrl\,rd<15:0>)
              -> (ed<7:0>,edrq2,eint\,rdy)

  land (ea0,erlr\) -> rd1
  land (edack2\,eiord\) -> rd2
  nor (rd1,rd2) -> oe\
  lnand (rd1,erlr\) -> rs\
  tsbuf (dav,rs\) -> ed<7>
  u74 (.L,wc\,.reset\,oe\) -> bit9,bit9\
  nand (dav,bit9) -> eint\
  and (dav,bit9\,edack2\) -> edrq2
  u74 (.L,ch\,.H,wdbrh\) -> hdav\,hdav
  u74 (.L,cl\,.H,wdbrl\) -> ldav\,ldav
  lor (ldav\,hdav\) -> dav
  land (ldav,hdav) -> rdy
  u74 (.L,ldav\,.H,oe\) -> h\,l\
  lnand (oe\,h\) -> eh\
  lnand (oe\,l\) -> el\
  lnor (.reset\,eh\) -> ch\
  lnor (.reset\,el\) -> cl\
  u374 (rd<15:8>,wdbrh\,eh\) -> ed<7:0>
  u374 (rd<07:0>,wdbrl\,el\) -> ed<7:0>
end

unit receiver (ea0,erlt\,ewlt\,edack3\,eiowr\,ed<7:0>,
       rdbr\,read,more)
           -> (ed<7>,edrq3,rcl,rcl\,rch,rch\,rh\,dav,dav\,td<15:0>)

  tsbuf (dav,erlt\) -> ed<7>
  lor (ewlt\,edack3\) -> w1
  lor (ewlt\,eiowr\) -> w2
  nand (w1,w2) -> w\
  and (ea0,edack3\,w1,w2) -> wc
  nor (read,more,.reset) -> cldav\
  u74 (.L,cldav\,.H,w\) -> rdy,dav1
  or (dav1,dav1)->dav2
$Optional c(dav2)->.gnd value 470pF
  or (dav2,dav2)->dav  inv (dav2) -> dav\
  and (rdy,cldav\,edack3\) -> edrq3
  nor (read,.reset) -> ceh\
  u74 (.L,ceh\,.H,more) -> el,eh
  lnand (w\,el) -> wh\
  lnand (w\,eh) -> wl\
  nand (wc,eh) -> wch\
  nand (wc,el) -> wcl\
  u74 (.L,wch\,.reset,rdbr\) -> rch,rch\
  u74 (.L,wcl\,.reset,rdbr\) -> rcl,rcl\
  inv (read) -> rword\
  u74 (.L,.reset\,.H,wh\) -> rh\,?
  u374 (ed<7:0>,wh\,rword\)  -> td<15:8>
  u374 (ed<7:0>,wl\,rword\)  -> td<7:0>
end

$ Interrupt vector and device address straps
$ Address bits are off for a one,
$ vector bits are on for a one.

  b16 (iv\<8:3>,.L,.L) -> biv\<8:3>,da<12:11>    at K76B
  b16 (.L,.L,.L,.L,.L,.L,.L,.L) -> da<10:3>      at K86B

$ Priority level straps
$ Connect bbgi<4:7> to bbgo<4:7>.
$ For priority level x, disconnect bbgo<x> from bbgi<x>,
$ then connect bbgi to bbgi<x>, and bbgo to bbgo<x>, and
$ bbr\ to bbr\<x>.

  b16 (bbgi<7:4>,bbgi,bbr\,?,bbr\<7>)
   -> (bbgo<7:4>,bbgo,bbr\<6:4>)    at N29B

$ Unibus transceivers

  xcvr (bd\<15:12>,td<15:12>,den\)
    -> (bd\<15:12>,rd<15:12>)  at N02B
  xcvr (bd\<11:08>,td<11:08>,den\)
    -> (bd\<11:08>,rd<11:08>)  at N11B
  xcvr (bd\<07:04>,td<07:04>,den\)
    -> (bd\<07:04>,rd<07:04>)  at M02B
  xcvr (bd\<03:00>,td<03:00>,den\)
    -> (bd\<03:00>,rd<03:00>)  at M11B

  xcvr (bssyn\,bbbsy\,bbgi,bnpgi, tssyn,tbbsy,.L,.L, .L)
    -> (bssyn\,bbbsy\,bbgi,bnpgi, rssyn,rbbsy,bgi\,npgi\)  at N38B

  xcvr (ba\<17:14>,mar<17:14>,dmaing\)
    -> (ba\<17:14>,ra<17:14>)  at N65B
  xcvr (ba\<13:10>,mar<13:10>,dmaing\)
    -> (ba\<13:10>,ra<13:10>)  at M65B
  xcvr (ba\<09:06>,mar<09:06>,dmaing\)
    -> (ba\<09:06>,ra<09:06>)  at M56B
  xcvr (ba\<05:02>,mar<05:02>,dmaing\)
    -> (ba\<05:02>,ra<05:02>)  at N47B
  xcvr (ba\<1>,bc\<1>,bmsyn\,binit\, mar<1>,txd,tmsyn,.L, dmaing\)
    -> (ba\<1>,bc\<1>,bmsyn\,binit\, ra<1>,rc<1>,rmsyn,binit)  at N56B

  r (bbgi)  -> .gnd  value 390
  r (bnpgi) -> .gnd  value 390
  r (.vcc)  -> bbgo  value 180
  r (.vcc) -> bnpgo  value 180
  lor (rinting\,tinting\) -> intr
  nand (intr,.H)  -> bintr\     on Dec8881  at L76B
  nand (intr,.H) -> iv\<8>      on Dec8881  at L76B
  nand (intr,.H) -> iv\<7>      on Dec8881  at L76B
  nand (intr,.H) -> iv\<6>      on Dec8881  at L76B
  nand (intr,.H) -> iv\<5>      on Dec8881  at L86B
  nand (intr,.H) -> iv\<4>      on Dec8881  at L86B
  nand (intr,.H) -> iv\<3>      on Dec8881  at L86B
  nand (intr,rinting\)  -> biv\<2> on Dec8881  at L86B
  nand (bgo\,bgo\)   -> bbgo       on Dec8881  at N20B
  nand (npgo\,npgo\) -> bnpgo  on Dec8881  at N20B
  nand (br,br)       -> bbr\   on Dec8881  at N20B
  nand (npr,npr)     -> bnpr\  on Dec8881  at N20B
  nand (tsack,tsack) -> bsack\ on Dec8881  at L65B

$ Device address recognition logic

  pu (.vcc) -> da<12>    Value 1K
  pu (.vcc) -> da<11>    Value 1K
  pu (.vcc) -> da<10>    Value 1K
  pu (.vcc) -> da<9>    Value 1K
  pu (.vcc) -> da<8>    Value 1K
  pu (.vcc) -> da<7>    Value 1K
  pu (.vcc) -> da<6>    Value 1K
  pu (.vcc) -> da<5>    Value 1K
  pu (.vcc) -> da<4>    Value 1K
  pu (.vcc) -> da<3>    Value 1K
  pu (.vcc) -> .h    Value 1K
  pu (.vcc) -> .h    Value 1K
  pu (.vcc) -> .h    Value 1K
  pu (.vcc) -> .h    Value 1K

  comparator (rmsyn,ra<17:13>,         ra<12,11>,
   .H,.H,.H,.H,.H,.H,da<12,11>,.L) -> sel\
  comparator (ra<10:3>,da<10:3>,sel\) -> select\
  nand (select\,select\) -> ssyn1  on Dec8881
  pu (.vcc) -> ssyn1  value 1K
  r (ssyn1) -> tssyn value 100
  c (tssyn) -> .gnd value 470p

  u155 (ra<2:1>,rc<1,1>,select\,select\)
    -> (wwcr\,wmar\,wdbr\,wcsr\, rwcr\,?,rdbr\,rcsr\)

  land (select\,rc<1>) -> busread
  land (rxd\,dmaing\) ->  dmaread
  nor (dmaread,busread) -> den\

$ MAR (Memory Address Register)

  u191 (.H,.H,rd<5,4>,.L,.L,wcsr\,mar\4)
    -> (?,?,mar<17,16>,?,?)
  u191 (.H,rd<15:13>,.L,.L,wmar\,mar\3)
    -> (?,mar<15:13>,?,mar\4)
  u191 (rd<12:09>,.L,.L,wmar\,mar\2)
    -> (mar<12:09>,?,mar\3)
  u191 (rd<08:05>,.L,.L,wmar\,mar\1)
    -> (mar<08:05>,?,mar\2)
  u191 (rd<04:01>,.L,.L,wmar\,count\)
    -> (mar<04:01>,?,mar\1)

$ WCR (Word Count Register)

  u191 (rd<15,15:13>,up\,wcz,wwcr\,wcr\3)
    -> (?,wcr<15:13>,min3,?)
  u191 (rd<12:09>,up\,wcz,wwcr\,wcr\2)
    -> (wcr<12:09>,min2,wcr\3)
  u191 (rd<08:05>,up\,wcz,wwcr\,wcr\1)
    -> (wcr<08:05>,min1,wcr\2)
  u191 (rd<04:01>,up\,wcz,wwcr\,count\)
    -> (wcr<04:01>,min0,wcr\1)
  u74 (rd<00>,.H,cwcr0\,wwcr\) -> wcrodd,wcreven

  inv (wcr<15>) -> up\
  nand (min0,min1,min2,min3) -> min\
  land (min\,wcr<15>) -> wcz
  and (wcz,wcreven) -> wcrz
  or (wcrz,tmo) -> dstop
  nor (wcrz,tmo) -> dstop\
  nand (wcz,dmaing,rssyn) -> cwcr0\
  nand (dmaing,rssyn) -> count\

  u244 (wcr<15:8>,rwcr\,rwcr\) -> td<15:8>
  u244 (wcr<7:1>,wcrodd, rwcr\,rwcr\) -> td<7:0>

$ CSR (Command and Status Register) - Status part

  u244 (rdy,ie,rch,rcl,dav,.L,tmo,wcrz, rcsr\,rcsr\) -> td<7:0>

$ CSR - Command part

  and (rd<1,0>) -> txde
  inv (rd<1>) -> rd1\
  and (rd1\,rd<0>) -> rxde
  u175 (rd<6>,txde,rxde,?, .reset,wcsr\)
    -> ie,txd,rxd,?, ?,?,rxd\,?

  inv (wcsr\) -> wcsr
  nand (wcsr,rd<3>) -> wc\
  and (wcsr,rd<7>) -> pinit
  nor (pinit,binit) -> .reset\
  inv (.reset\) -> .reset

$ Receiver

  nand (rxd,dmaing) -> rdmaing\
  lor (rdmaing\,rdbr\) -> read
  nand (rxd,dav,dstop\,rh\,rcl\,rch\,.H,.H) -> more\
  inv (more\) -> more
  nand (rxd,dstop) -> x1
  nand (dav\,rcl) -> x2
  nand (dav\,rch) -> x3
  nand (dav,rxd\) -> x4
  nand (dav,rh\,rch\) -> x5
  lor (x1,x2,x3,x4,x5,.H,.H,.H) -> ratn $ dstop.rxd+(rcl+rch+dav)&rdmr\
  nand (x4,x5,dav) -> rdmr\          $ rxd.dav.(rh+rch)

  receiver (ea0,erlt\,ewlt\,edack3\,eiowr\,ed<7:0>,
            rdbr\,read,more)
        -> (ed<7>,edrq3,rcl,rcl\,rch,rch\,rh\,dav,dav\,td<15:0>)

  acq (ratn,bgi\,rbbsy,rssyn)
   -> (rtsack\,?,rinting\,bgrt\,rbr)

$ Transmitter

  nand (dmaing,txd) -> tdmaing\
  lnand (tdmaing\,wcz) -> wdbrh\
  lnor (tdmaing\,wdbr\) -> wdbrl\
  nand (rdy,txd,dstop\) -> tdmr\
  nand (txd,dstop\) -> tbsy\
  and (tbsy\,rdy) -> tatn

  transmitter (ea0,erlr\,edack2\,eiord\,
               wc\,wdbrh\,wdbrl\,rd<15:0>)
           -> (ed<7:0>,edrq2,eint\,  rdy)

  acq (tatn,bgrt\,rbbsy,rssyn)
   -> (ttsack\,?,tinting\,bgo\,tbr)
  or (rbr,tbr) -> br

$ DMA logic

  u123 (.L,dmaing,dmaing,rctmo,ctmo) -> ?,stmo  value 10us
  r (.vcc) -> rctmo  on 74LS123
  c (rctmo) -> ctmo  on 74LS123
  u74 (dmaing,.H,wcsr\,stmo) -> tmo,?
  lor (tdmr\,rdmr\) -> datn
  or (rssyn,tmo) -> dssyn
  acq (datn,npgi\,rbbsy,dssyn)
   -> (dtsack\,dmaing,dmaing\,npgo\,npr)
  lor (rtsack\,ttsack\,dtsack\) -> tsack
  lor (rinting\,tinting\,dmaing\) -> tbbsy
  or (.L,dmaing) -> d1
$ Optional c(d1) -> .gnd value 470pF
  and (dmaing,d1) -> tmsyn

end
finish
