A Guide to Understanding the Drawings
for the Ethernet Board (CSD142 Rev B)

RWT

Warning: Reading this document without a copy
of the drawings to hand can cause headache.

Version of 12/12/85

General

The 2MHz ethernet controller takes the form of a processor (Z80 CPU)
which controls the flow of data through four ports: Ether Transmitter,
Ether Receiver, Link Transmitter, Link Receiver.  A four-channel DMA
controller (Intel/NEC 8257) allows fast block transfers between any of
these ports and memory without the need to involve the CPU on a
byte by byte basis.  "Link" in this context refers to the parallel
interface to the boot processor's local bus (edge connector C).
This 9-bit wide interface consists of an 8-bit wide bidirectional buffer
register with various flags representing the "ninth bit", which indicates
whether the 8-bit character is in the DATA character set or the CONTROL
character set.

The four sheets of the drawing depict the processor/DMA pair, memory,
status registers, address decode and interrupt logic (sheet 1), the link
interface (sheet 2), the ether transmitter (sheet 3), and the ether
receiver (sheet 4).

Sheet 1 - Processor etc

In the top left corner we have the oscillator B13 which generates the
16 MHz master clock which makes everything happen.  Counter C13 divides
this down to produce the 4MHz clock for the CPU A10 and the DMA controller
A12.  E9.11 (near top left of CPU) is the combined memory select signal,
derived from the CPU's MREQ' (memory request) and the DMA's MR' and MW'
(memory read and memory write) signals.  Similarly, B11.6 is the combined
memory write signal.

The DMA controller does not have enough pins to generate all 16 address
lines, so requires a latch (B9, centre of drawing), to hold the upper 8
address bits.  Decoder B8, centre of drawing, generates the select signals
for the on-board memory, which consists of 4k bytes of EPROM (A1) and
12k bytes of static RAM (A3 to A9).  The actual configuration (mix of
memory chips) is as shown on the drawing, with a 2732 in A1 and 6116's
in the rest, but by modifying the wire links LK1 to LK7, it is possible
to plug in 2516-type EPROMs in place of either of these.

B12.2 (near bottom left corner of DMA) is low during DMA cycles, high
during CPU cycles.

Along the bottom of the drawing are boxes D9, G4, E4, D8, G5, and C2.
D9 generates the select signals for readable IO devices, D8 for writeable
ones, being enabled by B12.2 high (i.e. CPU cycle), the CPU's IORQ' signal,
and either the CPU's RD' or WR' signal.  They are fed with address bits
A6:A4, and so the following addresses select the following IO devices:

Read 00 and Write 00 access registers within the DMA controller, involving
B11.8, D10.3, D10.6 (to the left of D9).  This also explains why A6:A4 were
chosen to feed the decoders, it is because A3:A0 are used within the DMA
chip to address its internal registers (refer to the 8257 data sheet if
interested).

Read 10 does not actually read anything, it just has the side-effect of
clearing the DMA DONE interrupt flag, D13.8, triggered by the DMA's TC
(termination count) output.

Read 20 performs a Read Link Control operation (see later).

Read 30 performs a Read Link Data operation (see later).

Read 40 performs a Read Ether Receiver operation (see later).

Read 50 reads the Link Status Register (by enabling G4 onto the data bus).

Read 60 reads the Ether Status Register (by enabling E4 onto the data bus).

Read 70 and Write 70 have no effect.

Write 10 writes into the Interrupt Enable Register G5 which controls the
gates G6 to determine which maskable interrupts are allowed to happen.

Write 20 performs a Write Link Control operation (see later).

Write 30 performs a Write Link Data operation (see later).

Write 40 performs a Write Ether Receiver operation (see later).

Write 50 performs a Write Ether Transmitter Data operation (see later).

Write 60 performs a Write Ether Transmitter Control operation (see later).

C2 is enabled onto the data bus during interrupt acknowledge cycles, detected
by B6.3 (IORQ' with M1').  It generates the interrupt vector, which is an even
number in the range 02 to 0E, depending on which number in the range 1 to 7 is
supplied by the priority encoder F5.  The following interrupt conditions exist:

Vector 02: Link Transmitter Buffer Empty (lowest priority)
Vector 04: Link Receiver Data Ready
Vector 06: Link Receiver Control Ready
Vector 08: DMA Transfer Completed
Vector 0A: Ether Transmitter Done
Vector 0C: Ether Receiver Done
Vector 0E: Ether Receiver FIFO Overflow (highest priority)

The forst four of these can be disabled, which is essential in the case of
the first two if DMA transfers are to be possible from/to the link.

Sheet 2 - Link Interface

Along the bottom of the drawing we are reminded of the power and ground
connections on the various connectors.  Note connector A is the system
backplane, used only to obtain power (+5V for the logic, +12V for the tap,
-12V for the FIFO chips).  Connector C is for the front bus, the ribbon
cable over which the boot processor board communicates with this board.
Connector D is for the "garden hose" cable to the tap.

Along the right edge we have the connections to the boot processor, on
the left connections to the innards of the ether board.  Starting at top
right we have H2, G2, F7.12, G3, and H4.  G3 serves merely to buffer some
of the boot processor's signals.  H2, G2, and F7.12, in conjuntion with H4,
detect when the boot processor asserts an address within the range 7FFFC
to 7FFFF, with H4.5 (TP4) high when a transfer is requested on the upper
bus byte (D15 to D8), and H4.6 (TP5) high when a transfer is requested on
the lower bus byte (D7 to D0).  These two signals are combined with RW'
and A1 to generate various signals:

E9.3  is low during a lower bus write (to 7FFFD or 7FFFF) [Data or Control].
E9.6  is low during an upper bus write (to 7FFFC or 7FFFE) [Command].
F9.10 is low during any access [used to generate DTACK'].
G7.12 is low during a lower bus read (from 7FFFF) [Control].
G7.6  is low during a lower bus read (from 7FFFD) [Data].
E9.8  is low during an upper bus read (from 7FFFC or 7FFFE) [Status].

Flipflops E8 serve to delay DTACK for two clock cycles, and also to cut
off the write pulse early via F9.13 to ensure the data bus is still valid
and stable on the trailing egdes of E9.3/E9.6.

On the bottom right we have the status register E2 which may be read onto
the upper half of the boot processor's data bus.  The bits in it are as
follows:

7/15 high if the ether board is interrupting (TP7 high, C1.10 low).
6/14 high if the ether board is in the "being reset" state.
5/13 low always.
4/12 low always.
3/11 high when link transmitter ready.
2/10 high when link receiver contains a data character.
1/9  high when link receiver contains a control character.
0/8  high when link receiver contains any character.

Note that obviously what the Z80 sees as link TRANSMITTER is seen as link
RECEIVER by the 68000 and vice versa.

F8 is the command register, used by the 68000 to reset the ether board
and to enable (via G8.6/.8/.11) which of the conditions described by bits
3/11 to 1/9 of the status register are allowed to interrupt the 68000.
The command register has only four bits, and they occupy positions within
the byte which tie up with those in the status register.

Note the use of inverter F7.10 in the loop from data bus bit D14, through
F7.11/.10, F8.13/.14, E2.17/.16 back to D14.  This is such that the state
of the bit written into bit 6/14 of the command register (1 to reset, 0 to
operate) can be read back exactly the same in bit 6/14 of the status register.
Also output pin F8.15 has to be low to reset in order that the external
hardware reset (coming in on F8.1) puts the ether board into a reset
state initially.

Turning now to the left side of the drawing we have, in the middle, the
data holding and buffer registers F2 and F3.  The upper half of the left
side of the drawing (including F2) deals with data transfer from right to
left (68000 to Z80).  Flipflops H8 determine whether F2 holds a data or a
control character, while flipflop G9.6 is high when F2 is "empty".

The "write lower" signal from E9.3 appears at G9.4 thereby clearing the
"empty" condition.  It also appears at F2.11, thereby clocking data into F2,
and at H8.3 and H8.8 thereby setting either H8.5 or H8.9 depending on
the state of 68000 address bit A1 which determines whether the character
being written is data or control.

H9.11, when low, clears H8.5, which is the link receiver control ready
signal, high when F2 contains a control character; this clearing happens
as a result of either a RESET or a Read Link Control operation.

Similarly, H9.6, when low, clears H8.8, which is Link Receiver Data Ready,
high when F2 contains a data character; the clearing happens on RESET or
when the Z80 performs a Read Link Data operation (H9.1 low) or when the DMA
controller reads the data register (H9.2 low).  The Z80 link receiver is
associated with channel 2 of the DMA controller, and D14.11 generates a DMA
request whenever F2 contains data (but not control), but takes away the
request as soon as it sees DMA acknowledge (D14.13), to prevent the DMA
chip from using burst mode.

Lamp LD2 (top left as you look at the plugged-in board) comes on whenever
F2 contains data, but by changing jumper J2 it could be reconfigured to
come on when it contains control (1-3) or either control or data (1-2).

H9.8, when low, indicates that the Z80 (or the DMA) is performing a read
(either control or data), and so it enables F2 onto the Z80 data bus; it
also clocks G9.3, thereby setting the empty flag G9.6, subject to the
correct character being read: G8.3 sees to this, preventing EMPTY from
setting when the Z80 does a DATA read while F2 contains a CONTROL
character, or vice versa.

The control circuitry on the lower half of the left side of the drawing
is similar, but deals with data flow from left to right (Z80 to 68000).
F3 is the character holding register, F10.6 is high when F3 contains
control, F10.8 is high when F3 contains data, G9.8 is high when F3 is
empty.

G10.6 when low during reset or 68000 control read clears F10.6.
G10.11 when low during reset or 68000 data read clears F10.8.
G10.8 when low during 68000 control or data read enables F3 onto the
68000 data bus, and clocks G9.11 to clear G9.8, with E7.6 taking the
"wrong read" watchdog role, and also feeding bit 0/8 of the 68000
status register to indicate that F3 still contains either a data or
a control character.
G10.3 is low during Z80 control or data writes, and clears G9.8 and
clocks the Z80 data bus into F3.
F10.6 is set by Z80 control write (WLC').
F10.8 is set by Z80 data write (WLD') or DMA write (D12.11).
D11.3 generates the DMA request; the link transmitter is associated with
channel 3 of the DMA controller.

Sheet 3 - Ether Transmitter

Since the ether transmission data rate is 2M bits per second, the transmitter,
once started, must be supplied with a new byte of data every 4 microseconds.
The DMA controller is well able to cope with this rate on average, but is
unable to guarantee that sort of response instantaneously.  Therefore a FIFO
buffer is interposed between the Z80 data bus and the transmitter's shift
register (D4) instead of just a simple buffer register.

The FIFO consists of the lower two boxes on the left of the drawing (E3 and D3).
Each chip is only four bits wide and their input ready and output ready signals
are commoned-up with gates H6.11 (FIFO output ready) and E12.12 (FIFO input
ready).  Gate E7.8 generates the FIFO Shift In signal (as a result of Z80
write (WETD') or DMA write (channel 1)), flipflop H7.5 generates the FIFO
Shift Out signal; it is set by the byle clock (H7.3) provided the
transmitter is running at the time (H7.2 high), and cleared by FIFO output
not ready (H7.1 low).

The upper two boxes on the left of the drawing (B1, B2) constitute the
backoff delay counter, an 8-bit down counter into which the Z80 would
write (using WETC') the number of microseconds to wait before starting
to transmit the next packet (normally zero except after a collision).
circuitry, firstly via H6.8, which clears the DONE and COLLISION flags H5.8
and H5.5, and secondly via D6.12 and E5.8, which clears everything else.
Notice that when a collision occurs (H5.5 sets as a result of a transition
on H5.3 while the transmitter is active (H5.2 high)), this automatically
shuts down the transmitter via E5.9 and E5.8.

The backoff delay counter is allowed to count, via gate E11.12, provided
it is not already zero (E7.11, E11.13 high) and the transmitter has not
already started (E11.2 high), and the receiver has given permission to
transmit, having detected a silent period of adequate duration (E11.1 high).
Once this counter has reached zero, provided the receiver has not withdrawn
its permission to transmit, and the transmitter has not yet started, E12.6
comes on.  This signal indicates "start transmitter when ready", the
transmitter will then start as soon as data appear at the output of the FIFO;
gate E11.6 then generates a low-going "start transmitter now" pulse.

Flipflops E13 and E14 control the operation of the transmitter.  Assuming
there are no collisions, which would stop the transmitter dead, the
transmitter will proceed with sending a packet as follows:  Start as soon
as the first byte appears on the FIFO output (the first byte is actually
sent twice, the remaining bytes once).  When the FIFO output is not ready
by the time the next byte is required, the transmitter assumes this is the
end of the (data part of the) packet and begins an orderly shutdown by
appending a 16-bit checksum.

E13.5 (TP10) is high during the data portion of the packet and turns low
to switch into CRC mode.  One byte-time later E13.9 goes low, and after a
further byte-time, E14.5 goes low, causing the bit stream into flipflop
D13.5 which feeds the "garden hose" line driver G13 to be shut off; at
the same time the DONE flag (H5.8) sets, generating an interrupt to the
Z80.  After another byte time E14.9 goes low, extinguishing the "transmitting"
lamp LD3 (top right).

Turning now to the bit stream processing, the serial data emerge from
shift register D4.9 and are fed to the Manchester encoder (xor gate D7.5).
[A Manchester encoded signal consists of a sequence of bit cells in which
there is always a transition in the middle of each bit cell, there may or
may not be transitions at bit cell boundaries.  The direction of the
transition in the middle (rising/falling) determines the state of the
bit being transmitted (zero/one).  Looked at in another way, the first half
of each bit cell contains the state of the bit (one=high, zero=low), the
other half is always the opposite.].  Thus, as D7.4 has a 2MHz square
wave on it, D7.6 contains the Manchester-encoded version of D7.5, which
is synchronized in flipflop D13.5.

The shift register output is also fed to the 8X01 CRC generator/checker
G11.  This chip, as it is shared between receiver and transmitter, is fed
via multiplexor G12.  When G12.1 is high, the 8X01 belongs to the
transmitter, otherwise to the receiver.  Multiplexor E10 determines
whether the Manchester encoder is fed from the shift register (upper gate)
or from the CRC generator (lower gate).  Flipflops F12 serve to synchronise
various signals for the CRC generator.

On the bottom right of the drawing we have counters F13 and F11, which,
together with D14.3 and B10.5, generate various timing signals.  Whenever
the transmitter is running, the following signals may be observed:

F13.14: 8 MHz square wave
F13.12: 2 MHz square wave [bit clock]
D14.3:  4 MHz square wave with 25% duty cycle [2x bit clock for Manch enc]
F13.15: 1 MHz pulses (60ns wide)
F11.15: 250 kHz pulses (1us wide)
B10.5:  250 kHz pulses (60ns wide) [byte clock]

Sheet 4 - Ether Receiver

As with the ether transmitter, the receiver contains a FIFO to reduce the
urgency requirement from the DMA response time.  The data FIFO consists of
C4 and C5, with E6 providing an extra 3 bits of control information with
each character.  CONTROL (E6.13) is high if end-of-packet has been detected,
and in this case the outputs of C4 and C5 are meaningless and ERCRC and
ERCOL (E6.12 and E6.11) are meaningful and indicate, if high, that the
current packet contained a CRC error or was stopped due to a collision
[The receiver detects collisions by seeing the state of the line as high
when transitions cease; transmitters detecting collisions will jam the
ether for a few microseconds to ensure that all transmitters involved in
the collision notice.  If you can't find the jam circuitry on sheet 3,
don't panic, the logic to do this is contained in the tap.].  When CONTROL
is low, ERCRC and ERCOL are meaningless and the data outputs of C4 and C5
are meaningful.  C3 (two boxes) provide tristate drive capability to allow
the FIFO outputs to be put onto the Z80 data bus.

Gates C6.8 and C6.6 generate the combined FIFO Input Ready and FIFO
Output Ready signals.  E7.3 generates interrupting signal ERDONE'
when a control character appears at the FIFO output.  When a data character
appears at the FIFO output, a DMA request is generated by flipflop B10.8.
H6.6 is low during a FIFO read, which for data characters is always done
by the DMA controller (H6.4 low) and for control characters by the Z80
(H6.5 (RER') low).  RER' low has the side-effect of clearing the FIFO
overflow flag.  Flipflop H7.8 generates FIFO shift out signal, while
flipflop F6.5 generates the FIFO shift in signal, which is triggered
whenever there is a rising edge on TP16, the byte clock.  If at this point
the FIFO input is not ready, this indicates that the FIFO is full and
unable to accept the byte currently in the shift register B5, and so the
FIFO overflow flag (F6.8) sets, which generates an interrupt and has the
side-effect of clearing down the FIFO completely.  The FIFO can also be
cleared under program control, when the Z80 asserts WER', which writes into
the filter register B3, because it has the side-effect of setting the overflow
flag.

The first byte in every packet (the one that is sent twice) is the destination
station address, it is normally in the range 01 to 7F; value 00 denotes a
broadcast, values 80 to FF are not possible [this is because packets are
transmitted without a preamble, most significant bit first, and the first
(rising) transition after silence is assumed to be the middle of the first
bit cell, which is therefore assumed by the receiver to be zero.  If a
transmitter were so daft as to transmit a packet beginning with a byte in the
range 80 to FF, all receivers would misinterpret the packet one half bit out of
phase.].  So as not to overwork the Z80's in all the receivers, each of them
contains an address filter whose job it is to inspect the first byte of every
packet (in hardware) and to determine whether the packet should be let in.
Flipflop C8.6, RECEIVING, is turned on by C8.3 (which rises when the
receiver has seen the whole of the first byte), provided at least one of
the three conditions feeding E5.6 applies, otherwise no data are clocked
into the FIFO since RECEIVING is a qualifying input to flipflop F6.5.

These three conditions are: (1) Address Match (E5.4 high): The comparator
B4 has found that the current character in shift register B5 (the destination
address in the packet) is the same as the low-order 7 bits in B3 (the
receiving station's address). (2) The receiver is operating in what has become
known as "promiscuous mode" (E5.3 high), i.e. is prepared to accept all
packets no matter to where they are addressed.  Ethernet monitors would
exploit this feature, which is selected by setting the eighth bit of the
filter register.  (3) Broadcast (E5.5 high).  The destination address in
the packet is zero.  This is detected by the flipflop formed by cross-coupled
gates D5.6/D5.8, which is set by a low on D5.4 (during silence) and cleared
by a low on D5.10 (whenever a "one" data bit is seen.

Now for the difficult bit...

The DATA IN signal from the tap is amplified by line receiver H13, and the
resulting "clean" signal (TP17) is fed into latch C7, used here as two
3-bit shift registers.  The first stage (C7.2) synchronises the incoming signal
to the local clock; the second stage (C7.5) delays it by one clock "for good
measure",  The third stage (C7.7) and the second stage thus guarantee to view
the incoming signal one clock-time (1/8 bit-time) apart.  As they feed xor
gate D7.3, we obtain a low-going pulse of 1 clock duration at D6.6, whenever
any transition in the ether signal is seen.  Flipflop C8.9 (TP18) generates
the fourth stage data signal, which in turn feeds the character shift register
B5, clocked by the signal-derived clock (TP19).  The lower 3 stages of C7
generate delayed versions of the transition pulse, but only those transitions
occurring in the middle of a bit-cell, as determined by "clock window"
generator gate C12.6.  Each time a clock transition is detected, shift
register C11 is cleared, but the pulse ripples through two stages in C7,
and then through the whole of C11.  If a new transition occurs while the
previous pulse has reached pin 5, 6, 10, or 11 of C11, it is treated as a
new clock pulse and C11 is cleared again.  If no new transition is seen by
the time the previous pulse has reached C11.13, we assume the end of packet
has been reached.  This triggers the flipflop consisting of cross-coupled
gates C10.13 and E5.12.  Before and during packet reception, E5.12 is low
and C10.13 is high.  At the end-of-packet this reverses.

Multiplexor E10 generates the byte clock which feeds the FIFO.  Normally
the lower gate is relevant; a delayed bit clock (E10.10/E10.11) is passed
through, provided E10.9 is high (which is the case when counter C9 has
counted 15 data bits, indicating that almost two characters (the same two)
have been received.  Incidentally, C9.11 goes high after the first
character has been seen, thus clocking the RECEIVER flipflop).  Once
silence has been detected, C9 is cleared and the upper half of E10 passes
through a 1 MHz clock from counter H12 which guarantees that control
characters are pumped into the FIFO.

H11.4 goes high after at least 2 us of silence, and H10.4 goes high after
at least 4 us of silence provided the FIFO is empty, thus giving the
transmitter the go-ahead to transmit if it should so wish.

"I wish I could understand how this damn thing works!" said the author.
