! Include file for APM SCSI interface Mk1 (non-DMA)
! RWT November 1986

! The board contains two NCR5380 controllers, one connected
! to byte 0, the other to byte 2 of the system bus.
! Decoding logic responds to addresses in the range 16_00FDXXXX,
! address bits 4:2 select the registers within the chip.
! The chips are selected using either the CS pin or the DACK pin,
! depending on whether the access is by word (both CO0 and CO1
! (or CO2 and CO3) active together) or by byte (only CO0 or CO2
! active), respectively.  Byte accesses using CO1 or CO3 have the
! effect of resetting both controllers.

%option "-low-nonstandard"

%recordformat ncr5380(%byte dma                      %or-
  (%readonlyhalf  csd,  {current scsi data}          *,
                  {icr}                            *,*,
                  {mode}                           *,*,
                  {tcr}                            *,*,
                  cbs,  {current bus status}         *,
                  bsr,  {bus and status register}    *,
                  idr,  {input data register}        *,
                  rpi,  {reset parity/interrupt}     *) %or-
  (%writeonlyhalf odr,  {output data register}       *,
                  {icr}                            *,*,
                  {mode}                           *,*,
                  {tcr}                            *,*,
                  ser,  {select enable register}     *,
                  sds,  {start dma send}             *,
                  str,  {start target receive}       *,
                  sir,  {start initiator receive}    *) %or-
  (%half          {csd/odr}                        *,*,
                  icr,  {initiator command register} *,
                  mode, {mode register}              *,
                  tcr,  {target command register}    ))
                 
@16_fd0000 %record (ncr5380) chip0
@16_fd0002 %record (ncr5380) chip1

%constinteger -
icr rst  = 16_8000, {assert RST
icr aip  = 16_4000, {arbitration in progress (also TEST MODE)
icr lost = 16_2000, {arbitration lost
icr ack  = 16_1000, {assert ACK
icr bsy  = 16_0800, {assert BSY
icr sel  = 16_0400, {assert SEL
icr atn  = 16_0200, {assert ATN
icr data = 16_0100  {enable data drivers

%constinteger -
mode blk = 16_8000, {block mode dma
mode tgt = 16_4000, {target mode
mode epc = 16_2000, {enable parity checking
mode epi = 16_1000, {enable parity interrupt
mode eop = 16_0800, {enable eop interrupt
mode bsy = 16_0400, {monitor bsy
mode dma = 16_0200, {dma mode
mode arb = 16_0100  {arbitrate

%constinteger -
tcr req = 16_0800, {assert REQ
tcr msg = 16_0400, {assert MSG
tcr cd  = 16_0200, {assert CD (1 for C, 0 for D)
tcr io  = 16_0100, {assert IO (1 for I, 0 for O)
tcp out = 16_0000, {expected(initiator) or selected(target) phases
tcp in  = 16_0100,
tcp cmd = 16_0200,
tcp sta = 16_0300,
tcp mso = 16_0600,
tcp msi = 16_0700,
tcp mask = 16_700

%constinteger-
cbs rst = 16_8000, {states of actual bus signals}
cbs bsy = 16_4000,
cbs req = 16_2000,
cbs msg = 16_1000,
cbs cd  = 16_0800,
cbs io  = 16_0400,
cbs sel = 16_0200,
cbs dbp = 16_0100

%constinteger-
bsr end = 16_8000, {end of dma
bsr drq = 16_4000, {dma request
bsr par = 16_2000, {parity error
bsr irq = 16_1000, {interrupting
bsr pha = 16_0800, {phase match
bsr bsy = 16_0400, {busy error
bsr atn = 16_0200,
bsr ack = 16_0100

