      ttl Ether Board Checkout Aid

* This part runs on the boot processor
* modified 18/02/86 to double-check when
* finding inconsistent CSR status.

      bin
      org $1000

pend equ $3ed0
      dc.l $3ed0   * SP
      dc.l begin   * PC
      dc.l buserr
      dc.l adderr
  dc.l zap     * 010
  nolist
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 020
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 030
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 040
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 050
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 060
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 070
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 080
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 090
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 0a0
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 0b0
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l psym    * 0c0
  dc.l pstring
  dc.l rsym
  dc.l nsym
  dc.l zap     * 0d0
  dc.l tsym
  dc.l zap
  dc.l zap
  dc.l zap     * 0e0
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 0f0
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 100
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 110
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 120
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 130
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 140
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 150
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 160
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 170
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 180
  dc.l zap
  dc.l zap
  dc.l nhex
  dc.l bhex    * 190
  dc.l whex
  dc.l phex
  dc.l rhex
  dc.l zap     * 1a0
  dc.l zap
  dc.l zap
  dc.l zap
  dc.l zap     * 1b0
  dc.l zap
  dc.l zap
  dc.l zap
  list
  dc.l zap     * 1c0

cr    equ 13
lf    equ 10

vdus  equ $4000c1
vdud  equ $4000c3
vinit equ 3
vmode equ $11

space moveq #' ',d0
      bra.s psym
newline moveq #cr,d0
      bsr.s psym
      moveq #lf,d0
psym  btst.b #1,vdus     * Send D0 (preserved) to VDU
      beq psym
      move.b d0,vdud
      rts

print macro
\*    bsr ptext
      dc.b \1,0
      ds.w 0
      endm

ptext move.l (sp)+,a0
pt1   move.b (a0)+,d0
      beq.s pt2
      bsr psym
      bra pt1
pt2   moveq #1,d0
      add.l a0,d0
      bclr #0,d0
      move.l d0,a0
      jmp (a0)

pstring move.b (a0)+,d1
pstr1 subq.b #1,d1
      beq.s pstr2
      move.b (a0)+,d0
      bsr psym
      bra pstr1
pstr2 rts

phex  move d0,-(sp)
      swap d0
      bsr.s whex
      move (sp)+,d0
whex  move d0,-(sp)
      ror #8,d0
      bsr.s bhex
      move (sp)+,d0
bhex  move d0,-(sp)
      lsr.b #4,d0
      bsr.s nhex
      move (sp)+,d0
nhex  move d0,-(sp)
      and #15,d0
      cmp #9,d0
      ble.s nh1
      addq #7,d0
nh1   add #'0',d0
      bsr psym
      move (sp)+,d0
      rts

rsym  lea pend,a0
      move.w (a0),d0
      move.w #-1,(a0)
      ext.l d0
      bmi.s rsym1
      rts
rsym1 move.b vdus,d0
      btst #0,d0
      beq.s rsym1
      moveq #127,d0
      and.b vdud,d0
      bra psym

nsym  lea pend,a0
      move.w (a0),d0
      ext.l d0
      bmi.s nsym1
      rts
nsym1 bsr rsym1
      move.w d0,(a0)
      rts

ssym  lea pend,a0
      move.w #-1,(a0)
      rts

tsym  move.b vdus,d0
      btst #0,d0
      bne rsym
      moveq #-1,d0
      rts

rhex  clr.l d1
      bsr nsym
      cmp #' ',d0
      bgt.s rh1
      bsr rsym
      bra rhex
rh1   cmp #'0',d0
      blt.s rh9
      cmp #'9',d0
      ble.s rh2
      and #95,d0
      cmp #'A',d0
      blt.s rh9
      cmp #'F',d0
      bgt.s rh9
      subq #7,d0
rh2   sub #'0',d0
      lsl.l #4,d1
      add d0,d1
      bsr rsym
      bsr nsym
      bra rh1
rh9   move.l d1,d0
      rts

*
*  M A I N   P R O G R A M
*

begin reset
      move.w #$2700,sr
      move.w #$0080,$080000  * Initialise map reg 0
      move.b #vinit,vdus     * Initialise ACIA
      move.b #vmode,vdus
      print <cr,lf,'Starting',cr,lf>
      bra start

zap   print <cr,lf,'Unexpected trap'>
die   print <' sr='>
      move.w (sp),d0
      bsr whex
      print <' at '>
      move.l 2(sp),d0
      bsr phex
hang  move.b vdud,d0
      bsr ssym
      bsr rsym
again moveq #-1,d0
      dbra d0,*
      move.l 0,sp
      move.l 4,-(sp)
      move.w #$2700,-(sp)
      rte

fct   dc.b 'f0udupf3f4sdspia'

buserr print <cr,lf,'Bus'>
bae   print <' Error '>
      moveq #$10,d0
      and.b 1(sp),d0
      beq.s bae1
      move.b #'R'-'W',d0
bae1  add.b #'W',d0
      bsr psym
      moveq #8,d0
      and.b 1(sp),d0
      beq.s bae2
      moveq #'N',d0
      bsr psym
bae2  moveq #7,d1
      and.b 1(sp),d1
      add.b d1,d1
      lea fct,a0
      move.b (a0,d1),d0
      bsr psym
      move.b 1(a0,d1),d0
      bsr psym
      bsr space
      move.l 2(sp),d0
      bsr phex
      bsr space
      move.w 6(sp),d0
      bsr whex
      addq.l #8,sp
      bra die

adderr print <cr,lf,'Address'>
      bra bae

ethcsr equ $7fffc
ethdcr equ $7fffd
ethccr equ $7ffff

sendwait move d0,-(sp)
      moveq #8,d0
      and.b ethcsr,d0
      bne.s sendw9
      print <7,'busy',cr,lf>
sendw1 moveq #8,d0
      and.b ethcsr,d0
      beq sendw1
sendw9 move (sp)+,d0
      rts

csrswitch1 dc.l ridle,rtry,rtry,rc,rtry,rd,rtry,rtry
csrswitch2 dc.l ridle,rerr,rerr,rc,rerr,rd,rerr,rerr

start move.b #$40,ethcsr
      move.b ethcsr,d1
      cmp.b #$48,d1
      beq.s st1
      print <'CSR during reset is not 48 but '>
      move.b d1,d0
      bsr bhex
      bsr newline
st1   move.b #0,ethcsr
      move.b ethcsr,d1
      cmp.b #8,d1
      beq.s st2
      print <'CSR after reset is not 08 but '>
      move.b d1,d0
      bsr bhex
      bra.s ridle
st2   print <'CSR OK',cr,lf>
ridle bsr tsym
      bmi.s st5
      cmp.b #'^',d0
      beq.s sctrl
      cmp.b #'_',d0
      beq.s sbin
      cmp.b #'Y'-64,d0
      beq again
send  bsr sendwait
      move.b d0,ethdcr
      bra.s st5
sbin  bsr rhex
      bsr ssym
      bra send
sctrl bsr rhex
      bsr ssym
      bsr sendwait
      move.b d0,ethccr
st5   move.b ethcsr,d1
      moveq #7,d0
      and d1,d0
      add d0,d0
      add d0,d0
      lea csrswitch1,a0
      move.l (a0,d0),a0
      jmp (a0)
rtry  move.b ethcsr,d1
      moveq #7,d0
      and d1,d0
      add d0,d0
      add d0,d0
      lea csrswitch2,a0
      move.l (a0,d0),a0
      jmp (a0)
rerr  print <'CSR has inconsistent RX status '>
      move.b d1,d0
      bsr bhex
      bra hang
rd    move.b ethdcr,d1
      cmp.b #lf,d1
      beq.s rdnl
      cmp.b #' ',d1
      blt.s rdh
      cmp.b #'~',d1
      bgt.s rdh
      move d1,d0
      bsr psym
      bra ridle
rdh   moveq #'_',d0
      bsr psym
      move d1,d0
      bsr bhex
      bra ridle
rdnl  bsr newline
      bra ridle
rc    move.b ethccr,d1
      bsr newline
      moveq #'^',d0
      bsr psym
      move d1,d0
      bsr bhex
      bra ridle

      end
