\contentsline {section}{\numberline {1}Introduction}{5}
\contentsline {section}{\numberline {2}Logic Design}{7}
\contentsline {subsection}{\numberline {2.1} Introduction}{7}
\contentsline {subsection}{\numberline {2.2} The ED500 ULA Cell}{7}
\contentsline {subsection}{\numberline {2.3} The Four Bit Chained Adder}{9}
\contentsline {subsubsection}{\numberline {2.3.1} A Closer Look at the Adder}{9}
\contentsline {subsubsection}{\numberline {2.3.2}The Adder Logic Circuit}{11}
\contentsline {subsection}{\numberline {2.4} The Comparators}{13}
\contentsline {subsubsection}{\numberline {2.4.1} Approach }{13}
\contentsline {subsubsection}{\numberline {2.4.2} A General One Bit Comparator}{13}
\contentsline {subsubsection}{\numberline {2.4.3} The Greater and Less Than Comparators}{15}
\contentsline {section}{\numberline {3}The Limits' Programmablity}{19}
\contentsline {section}{\numberline {4}Feasibility}{21}
\contentsline {subsection}{\numberline {4.1}Gate Array Layout}{21}
\contentsline {subsection}{\numberline {4.2}Gate Array Performance}{22}
\contentsline {section}{\numberline {5}Testing}{26}
\contentsline {subsection}{\numberline {5.1} Pre Fabrication Testing}{26}
\contentsline {subsection}{\numberline {5.2}Post Fabrication Testing}{27}
\contentsline {section}{\numberline {6}Project Management}{28}
\contentsline {subsection}{\numberline {6.1}Hours Spent}{28}
\contentsline {subsection}{\numberline {6.2}Costing}{29}
\contentsline {section}{\numberline {7}Improvements}{30}
\contentsline {subsection}{\numberline {7.1}Layout}{30}
\contentsline {subsection}{\numberline {7.2}Timing}{30}
\contentsline {section}{\numberline {8}Conclusions}{31}
\contentsline {section}{\numberline {9}Appendix A}{32}
\contentsline {section}{\numberline {10}Appendix B}{33}
\contentsline {section}{\numberline {11}Appendix C}{34}
