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$pages
$chapter'Framestore'
$p0
The framestore consists of 2 types of circuits:
$b1
$item[display memory circuit corresponding to a 1024x1024
array of bits for the display, together with an associated 16-bit video
shift register
]$b0.5
$item[memory control circuit, responsible for the timing of the
write operations
in the display memory as well as for displaying of its contents on the screen
]
$b0.5 $picture('Framestore and its interface',4.4")
$14$u[Display memory]
$p1
There are 4 memory circuits on one board, and they can be configured as:
$b0.5
$item[4 planes with 1024x1024 pixels at 25MHz
]$b0.5
$item[2 planes with 2048x1024 pixels at 50MHz
]
$b1
$14$u[Display memory control circuit]
$p1
The display memory control circuit can control frames with up to 16 planes 
(16 bits/pixel).
The interface to the circuit has the following form:  
$b1
$item[two 12-bit coordinate addresses: $i[X<11:0>] and $i[Y<11:0>]
]$b0.5
$item[16-bit data bus: $i[D<15:0>]
]$b0.5
$item[handshake lines to implement synchronisation with the processor 
driving the framestore
]
$p0.5
The circuit includes the following processor writeable frame control registers:
$b0.5
$item[$h[colour register] for holding the colour to be used during write
operations into the frame
]$b0.5
$item[$h[plane write enable register], holding a mask of planes 
with permitted write operation
]$b0.5
$item[$h[X offset register] specifying the horizontal position of 
the left edge of the monitor display window within the frame
]$b0.5
$item[$h[Y offset register] specifying the vertical position of the display
window within the frame
]
$b0.5
Offset registers are used for selecting parts of a picture for display
when the frame size exceeds that of the monitor. They also permit the use
of a double-buffering technique during image calculation where the frame size
is at least twice as large as the viewable area.
$b0.5 $picture('A sequence of write operations to draw an "a"',4")
A write access into the framestore puts the contents of the colour register
into all pixels indicated by 1's on framestore data bus, where bits 
$i[D<15:0>] are positioned from ($i[X<11:0>,Y<11:0>]) to
($i[X<11:0>]+15$i[,Y<11:0>]) in the framestore.
$E*
