$ 10 MHz Ethernet interface for Gateway APM
$ RWT January 1985

unit lance

(.gnd,.gnd,.gnd,.gnd,.gnd,.gnd,
.vp12,.vp12,.vp12,.vm12,.vm12,.vm12,
co'<3:0>,
bgr',rst',tac',trq',
.gnd,.gnd,.vp12,
coll,coll',rec,rec',
.vm5,.vm5,.vm5,.vcc,.vcc,.vcc) ->
(ad'<2:31>,
da<30:37,20:27,10:17,0:7>,
r\w',
brq',cbr',
trans,trans')

on eurozap2g

pins (
a01a,a01b,a01c,a02a,a02b,a02c,           $ .gnd
a03a,a03b,a03c,a04a,a04b,a04c,           $ .vp12,.vm12
a16a,a15c,a15b,a15a,                     $ co'<3:0>
a17c,a18a,a19a,a19c,                     $ bgr',rst',tac',trq'
d1,d6,d13,                               $ Shield,Ground,Power
d2,d9,d5,d12,                            $ coll,rec
a31a,a31b,a31c,a32a,a32b,a32c,           $ .vm5,.vcc
a05a,a05b,a05c,a06a,a06b,a06c,           $ ad'<2:7>
a07a,a07b,a07c,a08a,a08b,a08c,a09a,a09b, $ ad'<8:15>
a09c,a10a,a10b,a10c,a11a,a11b,a11c,a12a, $ ad'<16:23>
a12b,a12c,a13a,a13b,a13c,a14a,a14b,a14c, $ ad'<24:31>
a20b,a20c,a21a,a21b,a21c,a22a,a22b,a22c, $ da<3*>
a23a,a23b,a23c,a24a,a24b,a24c,a25a,a25b, $ da<2*>
a25c,a26a,a26b,a26c,a27a,a27b,a27c,a28a, $ da<1*>
a28b,a28c,a29a,a29b,a29c,a30a,a30b,a30c, $ da<0*>
a16c,a17a,a17b,                          $ r\w',brq',cbr'
d3,d10)                                  $ trans

define land=nor
define lor=nand

spec u74 (d,s',r',c) -> q,q'
spec u125 (i,e') -> o
spec u175 (d<1:4>,clr',ck) -> q<1:4>,q'<1:4>
spec u240 (i<3:0>,e') -> o'<3:0>
spec u244 (i<3:0>,e') -> o<3:0>
spec u245 (i<7:0>,otoi'itoo,e') -> o<7:0>
spec u373 (d<7:0>,e,oe') -> q<7:0>
spec u374 (d<7:0>,ck,oe') -> q<7:0>
spec u521 (a<1:8>,b<1:8>,stb') -> eq'
spec rom512x8 (a<8:0>,en') -> d<7:0>
spec carrier8 (x<1:8,16:9>)
spec lancechip (cs',adr,hlda',reset', rx,rclk,clsn,rena,tclk)
     -> (a<23:16>,dal<15:0>,bm'<1:0>,
         read,ale,das',hold',intr',ready',dalo',dali', tx,tena)
spec serialchip (tx,tena, coll,coll',rec,rec', x1,x2, test',tsel,pf,rf)
     -> (rx,rclk,clsn,rena,tclk, trans,trans')

$ Crystal, pullups (not explicit)

$ xtal -> x1,x2  value 20MHz                         +-------------------+
$ c (x1) -> .gnd value 100pF                         | A a               |
$ c (x2) -> .gnd value 100pF                         | B b            Bus|
$ c (.gnd) -> pf value .1uF                          | C c           Conn|
$ c (.gnd) -> rf value .1uF                          | D d               |
$ c (.vcc) -> .gnd value .1uF                        |                   |
$ c (.vcc) -> .gnd value 5uF                         | E e               |
$ r (.vcc) -> tsel value 2k                          |                   |
$ r (tsel) -> tsc  value 2k                          |                   |
$ c (tsc) -> .gnd  value 470pF                       |                Tap|
$ pu1k -> ready'                                     |               Conn|
$ pu1k -> das'                                       +-------------------+
$ Extra pullups as follows for constants to feed 240's          Switch Position
$ ICO<3:0>   determines which byte(s) strobed during int       =8      e
$ IA<31:24>  determines high address byte for int and dma      =00     ab
$ IA<23:13>  determines which longword is addressed during int =FF7    cdE
$ IA<12>     determines mode (r'w) of int transaction          =1      E
$ BA<31:16>  determines board's slave address                  =00FE   ABCD
$ Switches ABCD are the LANCE board address
$ Switches abcd are the Boot Processor board address
$ Switch E is X + 2 * IntLevel (X=1 to enable, 0 to disable ints)
$ Switch e determines the interrupt byte (should be 8 for byte 3)

$ Transceiver cable termination (not explicit)

$ r (coll) -> comc value 39
$ r (coll')-> comc value 39
$ c (comc) -> .gnd value .1uF
$ r (rec)  -> comr value 39
$ r (rec') -> comr value 39
$ c (comr) -> .gnd value .1uF

$ Fancy chips

serialchip (tx,tena,coll,coll',rec,rec',x1,x2,.vcc,tsel,pf,rf)
        -> (rx,rclk,clsn,rena,tclk,trans,trans')

lancechip (cs',co<1>,hlda',reset',rx,rclk,clsn,rena,tclk)
       -> (a<23:16>,dal<15:0>,bm'<1:0>,
           read,ale,das',hold',intr',ready',?,?,tx,tena)

inv (tclk) -> 10mhz
inv (rst') -> reset
inv (reset) -> reset'

$ Address bus

$ DMA and Interrupt
u240 (ia<31:28>,master') -> ad'<31:28>   package 8
u240 (ia<27:24>,master') -> ad'<27:24>   package 8

$ Interrupt only
u240 (ia<23:20>,int') -> ad'<23:20>      package 3
u240 (ia<19:16>,int') -> ad'<19:16>      package 4
u240 (ia<15:12>,int') -> ad'<15:13>,r\w' package 5
u240 (ico<3:0>,int') -> co'<3:0>         package 1

$ DMA only
u240 (a<23:20>,hlda') -> ad'<23:20>                  package 3
u240 (a<19:16>,hlda') -> ad'<19:16>                  package 4
u240 (a<15:12>,hlda') -> ad'<15:12>                  package 5
u240 (a<11:08>,hlda') -> ad'<11:08>                  package 6
u240 (a<07:04>,hlda') -> ad'<07:04>                  package 6
u240 (a<03:02>,read,?,hlda') -> ad'<03:02>,mread',?  package 1
u373 (dal<15:8>,ale,lo) -> a<15:8>
u373 (dal<7:1>,dal1',ale,lo) -> a<7:2>,a1,a1'
inv (dal<1>) -> dal1'

$ Data bus

u245 (dal<07:00>,tobus,be3') -> da<37:30>
u245 (dal<15:08>,tobus,be2') -> da<27:20>
u245 (dal<07:00>,tobus,be1') -> da<17:10>
u245 (dal<15:08>,tobus,be0') -> da<07:00>
nand (co<3>,data) -> be3'  package 9
nand (co<2>,data) -> be2'  package 9
nand (co<1>,data) -> be1'  package 9
nand (co<0>,data) -> be0'  package 9
u240 (co'<3:0>,lo) -> co<3:0>            package 7
lor (slave',master') -> data
lor (slavedrive',masterdrive') -> tobus

$ Slave control logic

u521 (ad'<31:24>,ba'<31:24>,lo) -> sel3'
u521 (ad'<23:16>,ba'<23:16>,trq') -> sel2'
land (sel3',sel2') -> selected
u74 (selected,lockon',reset',10mhz) -> slave,slave'
u74 (slave,?,reset',10mhz) -> ?,cs'
land (cs',ready') -> slaveready
inv (slaveready) -> slaveready'
nand (slaveready',slave) -> lockon'
u125 (slave',cs') -> das'
nand (slave,slaveready) -> tac'  on ls38
u125 (r\w',slave') -> read
nand (slave,read) -> slavedrive'

$ Master control logic

u240 (byte<2,3,0,1>,hlda') -> co'<3:0>   package 7
land (bm'<0>,a1) -> byte<0>              package 2
land (bm'<1>,a1) -> byte<1>              package 2
land (bm'<0>,a1') -> byte<2>             package 2
land (bm'<1>,a1') -> byte<3>             package 2
u125 (read,hlda') -> r\w'
land (hlda',das') -> dtrq
nand (dtrq,dtrq) -> trq'  on ls38
u125 (tac',hlda') -> ready'
nand (hlda,mread') -> masterdrive'

$ Bus acquisition and interrupt control finite state machine

u374 (n<2:0>,tac',bgr',cbr',intr',hold',10mhz,lo) -> s<2:0>,i<2:0>,?,?
rom512x8 (s<2:0>,i<2:0>,intr',hold',reset',lo) -> n<2:0>,o<4:0>
u374 (o<4:0>,?,?,?,10mhz,lo) -> master',int',hlda',itrq,brq,?,?,?
nand (itrq,itrq) -> trq' on ls38
nand (brq,bgr') -> cbr' on ls38
inv (hlda') -> hlda
inv (brq) -> brq'

end

finish
