$ Chip library for LANCE 10MHz ethernet board

chip am7990 (cs',adr,hlda',reset', rx,rclk,clsn,rena,tclk, .vcc,.gnd,.gnd)
     -> (a<23:16>,dal<15:0>,bm'<1:0>,
         read,ale,das',hold',intr',ready',dalo',dali', tx,tena)
     on dil48
     pins (20,21,19,23, 31,27,28,30,25, 48,24,1,
           32,33,34,35,36,37,38,39,
           40,41,42,43,44,45,46,47,2,3,4,5,6,7,8,9,
           16,15, 10,18,14,17,11,22,13,12, 29,26)
     lancechip (cs',adr,hlda',reset', rx,rclk,clsn,rena,tclk)
     -> (a<23:16>,dal<15:0>,bm'<1:0>,
         read,ale,das',hold',intr',ready',dalo',dali', tx,tena)
end

chip am7991 (tx,tena, coll,coll',rec,rec', x1,x2, test',tsel,pf,rf,
            .gnd,.gnd,.gnd,.vcc,.vcc)
     -> (rx,rclk,clsn,rena,tclk, trans,trans')
     on dil24
     pins (10,12, 24,23,22,21, 8,9, 20,5,17,16,
           6,7,15, 19,18,
           2,4,1,3,11, 14,13)
     serialchip (tx,tena, coll,coll',rec,rec', x1,x2, test',tsel,pf,rf)
     -> (rx,rclk,clsn,rena,tclk, trans,trans')
end

$chip xyz8 (x<1:8,16:9>)
$  on dil16
$  pins (1,2,3,4,5,6,7,8,16,15,14,13,12,11,10,9)
$  carrier8 (x<1:8,16:9>)
$end

chip ls00(a1,b1,a2,b2,a3,b3,a4,b4,.vcc,.gnd)->y1,y2,y3,y4
      pins(1,2,4,5,9,10,12,13,14,7,3,6,8,11)
      on "dil14"
   nand(a1,b1)->y1
   nand(a2,b2)->y2
   nand(a3,b3)->y3
   nand(a4,b4)->y4
end

chip ls02(a1,b1,a2,b2,a3,b3,a4,b4,.vcc,.gnd)->y1,y2,y3,y4
      pins(2,3,5,6,8,9,11,12,14,7,1,4,10,13)
      on "dil14"
   nor(a1,b1)->y1
   nor(a2,b2)->y2
   nor(a3,b3)->y3
   nor(a4,b4)->y4
end

$chip ls04(a1,a2,a3,a4,a5,a6,.vcc,.gnd)->y1,y2,y3,y4,y5,y6
$      pins(1,3,5,9,11,13,14,7,2,4,6,8,10,12)
$      on "dil14"
$   inv(a1)->y1
$   inv(a2)->y2
$   inv(a3)->y3
$   inv(a4)->y4
$   inv(a5)->y5
$   inv(a6)->y6
$end

$chip s05(a1,a2,a3,a4,a5,a6,.vcc,.gnd)->y1,y2,y3,y4,y5,y6
$      pins(1,3,5,9,11,13,14,7,2,4,6,8,10,12)
$      on "dil14"
$   inv(a1)->y1
$   inv(a2)->y2
$   inv(a3)->y3
$   inv(a4)->y4
$   inv(a5)->y5
$   inv(a6)->y6
$end

chip ls38(a1,b1,a2,b2,a3,b3,a4,b4,.vcc,.gnd)->y1,y2,y3,y4
      pins(1,2,4,5,9,10,12,13,14,7,3,6,8,11)
      on "dil14"
   nand(a1,b1)->y1
   nand(a2,b2)->y2
   nand(a3,b3)->y3
   nand(a4,b4)->y4
end

chip ls74(d1,set'1,clr'1,ck1,d2,set'2,clr'2,ck2,.vcc,.gnd)->q1,q'1,q2,q'2
      pins(2,4,1,3,12,10,13,11,14,7,5,6,9,8)
      on "dil14"
   u74(d1,set'1,clr'1,ck1)->q1,q'1
   u74(d2,set'2,clr'2,ck2)->q2,q'2
end

chip ls125(i1,e'1,i2,e'2,i3,e'3,i4,e'4,.vcc,.gnd)->o1,o2,o3,o4
      pins(2,1,5,4,9,10,12,13, 14,7, 3,6,8,11)
      on "dil14"
   u125(i1,e'1)->o1
   u125(i2,e'2)->o2
   u125(i3,e'3)->o3
   u125(i4,e'4)->o4
end

chip ls240(i<7:0>,e'<4,0>,.vcc,.gnd) -> o'<7:0>
  pins(2,4,6,8,11,13,15,17, 1,19,20,10, 18,16,14,12,9,7,5,3)
  on dil20
  u240 (i<7:4>,e'<4>) -> o'<7:4>
  u240 (i<3:0>,e'<0>) -> o'<3:0>
end

chip ls240i(i<7:0>,.gnd,.gnd,.vcc,.gnd) -> o'<7:0>
  pins(2,4,6,8,11,13,15,17, 1,19,20,10, 18,16,14,12,9,7,5,3)
  on dil20
  inv (i<7>) -> o'<7>
  inv (i<6>) -> o'<6>
  inv (i<5>) -> o'<5>
  inv (i<4>) -> o'<4>
  inv (i<3>) -> o'<3>
  inv (i<2>) -> o'<2>
  inv (i<1>) -> o'<1>
  inv (i<0>) -> o'<0>
end

$chip ls244(i<7:0>,e'<4,0>,.vcc,.gnd)->o<7:0>
$  pins(2,4,6,8,11,13,15,17, 1,19,20,10, 18,16,14,12,9,7,5,3)
$  on dil20
$  u244(i<7:4>,e'<4>)->o<7:4>
$  u244(i<3:0>,e'<0>)->o<3:0>
$end

chip ls245 (i<7:0>,otoi'itoo,e',.vcc,.gnd) -> o<7:0>
  pins (9,8,7,6,5,4,3,2,1,19, 20,10, 11,12,13,14,15,16,17,18)
  on dil20
  u245 (i<7:0>,otoi'itoo,e') -> o<7:0>
end

chip ls373(i<7:0>,en,oe',.vcc,.gnd) -> o<7:0>
  pins(3,4,7,8,13,14,17,18, 11,1,20,10, 2,5,6,9,12,15,16,19)
  on dil20
  u373(i<7:0>,en,oe') -> o<7:0>
end

chip ls374(i<7:0>,ck,en',.vcc,.gnd) -> o<7:0>
  pins(3,4,7,8,13,14,17,18, 11,1,20,10, 2,5,6,9,12,15,16,19)
  on dil20
  u374(i<7:0>,ck,en')->o<7:0>
end

chip ls521(a<7:0>,b<7:0>,e',.vcc,.gnd)->eq'
  pins(2,4,6,8,11,13,15,17, 3,5,7,9,12,14,16,18, 1,20,10,19)
  on dil20
  u521(a<7:0>,b<7:0>,e')->eq'
end

chip $tbp$28s42 (a<9:1>,e',.vcc,.gnd) -> d<8:1>
  pins (19,18,17,16,5,4,3,2,1, 15, 20,10, 14,13,12,11,9,8,7,6)
  on dil20
  rom512x8 (a<9:1>,e') -> d<8:1>
end

$chip tbp24s41 (a<10:1>,e'<2:1>,.vcc,.gnd) -> d<4:1>
$  pins (15,16,17,1,2,3,4,7,6,5, 10,8, 18,9, 11,12,13,14)
$  on dil18
$  rom1kx4 (a<10:1>,e'<2:1>) -> d<4:1>
$end

finish
