Program  ex8_6 (input,output);

Const
   %include 'ilap:nmos.consts'

Type
   %include 'ilap:nmos.types'

Var
   bits, words : Integer;
   outfile : string [255];

%include 'ilap:nmos.specs'

   Procedure STACKchip (BITS, WORDS : Integer; OUTFILENAME : String[255]);
   
   Const
      mwid = 4; dwid = 2;   { metal & diffusion port widths }
      swid = 8;             { power supply width }
      topext = 8;          { extension of top route from stack }

   Var
      stx, sty, cox, coy, pucy, pocy, p1x, p2x, p3x, p4x : Integer;
      puy, poy : Array [1..16{bits}] Of Integer;
      ports    : Array [1..500{2*bits+8}] Of Connf;
      i  : integer;

   Begin
      initialise (OUTFILENAME);

      { Generate a stack of the required size }
      stack('Stack', bits, words, cox, coy, pucy, pocy,
             p1x, p2x, p3x, p4x, puy, poy);

      { Route all clock wires clear of other signal lines }
      symbol ('Top route');
         layer (metal);   width (4);
         wirey (p1x, 0, topext);
         wirey (p2x, 0, topext);
         wirey (p3x, 0, topext);
         wirey (p4x, 0, topext);
         width (swid);
         wirey (SX('Stack')-swid, -coy, coy+topext);
      endsymbol;

      { Route 2 pads from each side to the bottom }
      symbol ('Left route');
         layer (diffusion);
         for I := 1 to 4 do begin
            wirex (0, puy[i], -6*i);
            ay (0);
         end;
         for I := 5 to bits do begin
            wirex (0, puy[i], -24);
         end;
         wirex (0, pucy, -24);
         wirex (0, pocy, -24);
      endsymbol;

      { Add the component symbols together }
      symbol ('Chip inards');
         draw ('Left route', 0, 0);
         draw ('Stack', 0, 0);
         draw ('Top route', 0, sy('Stack'));
      endsymbol;

      { Set up pad routing and complete the chip }
      for I := 1 to 4 do begin
         fillport (ports[i], inpad, bottom, -6*i, dwid, diffusion);
         fillport (ports[i+bits], outpad, right, poy[i], dwid, diffusion);
      end;
      for i := 5 to bits do begin
         fillport (ports[i], inpad, left, puy[i], dwid, diffusion);
         fillport (ports[i+bits], outpad, right, poy[i], dwid, diffusion);
      end;
      fillport (ports[2*bits+1], inpad, left, pucy, dwid, diffusion);
      fillport (ports[2*bits+2], inpad, left, pocy, dwid, diffusion);
      fillport (ports[2*bits+3], inpad, top, p1x, mwid, metal);
      fillport (ports[2*bits+4], inpad, top, p2x, mwid, metal);
      fillport (ports[2*bits+5], inpad, top, p3x, mwid, metal);
      fillport (ports[2*bits+6], inpad, top, p4x, mwid, metal);
      fillport (ports[2*bits+7], vddpad, bottom, SX('Stack')-swid, swid, metal);
      fillport (ports[2*bits+8], gndpad, top, SX('Stack')-swid, swid, metal);
      placepads ('Stack chip', 'Chip inards', ports, 2*bits+8);
      finish;
   End;

Begin

   prompt ('Number of bits: ');
   readln (bits);
   if bits < 4 then begin
       Prompt ('Number of bits must be >= 4, please re-enter: ');
       repeat
          readln (bits);
       until bits>=4;
   end;

   prompt ('Number of words: ');
   readln (words);
   if words < 2 then begin
       Prompt ('Number of words must be >= 2, please re-enter: ');
       repeat
         readln (words);
       until words>=2;
   end;

   prompt ('File name for the chip: ');
   readln (outfile);

   Stackchip (bits, words, outfile);
End.