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\author{Hamish Dewar}
\title{ESDL}
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\section{Preamble}
ESDL design aids on APM \hspace{ 1.8 in} Hamish Dewar 06/06/83

The ESDL suite of circuit design programs is available on the APM. The
programs and related files are held in the Filestore directory ESDL:.

For a general description of the suite see Lee Smith's Departmental Report
"The Elementary Structural Description Language".

(The following text has been taken from the Vax: Some Vaxish references still
remain... \hspace{ 4.2 in} (JHB))

\section{The ESDL Suite}
ESDL is a suite of programs which assists with the construction of
digital hardware. The components of the ESDL system allow hardware to
be described textually, and allow these derscriptions to be
manipulated conveniently to produce construction schedules, simulation
traces, logic diagrams, and board drawings.
The ESDL suite can be accessed by first issuing the command:

\hspace*{ 0.7 in} SETUP ESDL

Those programs which use graphics (SKETCH, SHOWBOARD, VZAP) require the further
command
\\ \hspace*{ 0.7 in} SETUP EDWIN

before they can be used.

Programs of the suite are accessed by issuing the name of the
program followed by the input and output file specifications
separated by a slash.

Example: \hspace{ 0.2 in} $<$prog$>$ $<$in1$>$,$<$in2$>$,$<$in3$>$ / $<$out1$>$,$<$out2$>$,$<$out3$>$

A complete file specification is rarely required as each program in
the ESDL suite generates default file names or file extensions.
This is done by taking the root name of the first parameter, stripping off
the extension (if any) and adding an appropriate new one.
In the descriptions of individual programs that follow the defaults for
each stream will be given, for example:
Defaults: .SRC, .SRC, FRED.PRM / $<$root$>$.EIC, $<$root$>$.LIS
means that the extension .SRC is added to the file names specified
for input streams 1 and 2 if no extension is present. Input stream 3
defaults to FRED.PRM unless otherwise specified, and output
streams 1 and 2 have the root name with the extensions.EIC and .LIS
respectively, unless these streams are otherwise specified.

\section{ESDL}
Use the ESDL command to compile a hardware description
into the ESDL intermediate code. Input streams 1 and 2 are used for
ESDL source text. Stream 2 is read after stream 1 and only if stream 1
is not terminated by a FINISH statement. Compiled I-code is output
on output stream 1, and a listing file is produced on stream 2.

Defaults: .SRC,.SRC,DR0:[ESDL]ESDL.PRM/$<$root$>$.EIC,$<$root$>$.LIS

Examples:

\hspace*{ 0.7 in} \} ESDL UNIT
\\ \hspace*{ 0.7 in} \} ESDL S1,S2/S3.FIC,LIST
\\ \hspace*{ 0.7 in} \} ESDL TEST/.N,.TT

\section{DCODE}
Use the DCODE command to decode a compiled, flattened, packaged,
or placed description to a canonical form of the source
text. Compiling this source text should produce the same I-code
as has just been decoded.

Defaults: /.TT

Examples:

\hspace*{ 0.7 in} \} DCODE FRED.EIC
\\ \hspace*{ 0.7 in} \} DCODE UNIT.FIC/UNIT.LIS

\section{FLATTEN}
Flatten hierarchical descriptions, and link in externally compiled
unit descriptions. The unit to be flattened is input (in I-code)
on stream 1, and a library of 'external' units may be supplied on
stream 2 (also in I-code). The flattened and linked description
is output on output stream 1.

Defaults: .EIC/.FIC

Examples:

\hspace*{ 0.7 in} \} FLATTEN UNIT
\\ \hspace*{ 0.7 in} \} FLATTEN DESIGN,FLIPFLOPS.LIB/GATES

\section{PACKAGE}
The packaging program takes a compiled, flattened, element-level
description and a library of chip descriptions, and produces
a description in terms of chips (all elements packaged on chips
which contain them) and an updated element-level description
(information about the packaging now included). Input is on stream 1
and streams 2 and 3 are availbale for libraries (searched in that order).
Stream 3 defaults to the system's TTL7400 series library. Output
in terms of chips is produced on stream 1 and the updated input is
output on stream 2. Numerous diagnostic messages are produced at
the terminal.

Defaults: .FIC,,DR0:[ESDL]TTL74.LIB/.CIC

Examples:

\hspace*{ 0.7 in} \} PACKAGE DESIGN
\\ \hspace*{ 0.7 in} \} PACKAGE MYDESIGN,MYCHIPS.LIB/,MYDESIGN.UPD

(Note thet the system's TTL7400 library is accessed automatically)

\section{PLACE}
The placement program takes a circuit description in terms of chips,
a library describing the geometry of the packages in which these
chips are mounted, a library of standard board descriptions, and
produces a board on which all chips have been assigned positions.
An updated form of the input is output on stream 2
(the input with positions for each chip inserted). A list of all
the pre-wired signals (such as power and ground) which have to be
cut is produced on output stream 3 and at the terminal.
By default input stream 2 takes the standard library of packages which
contains all the commonly used dual inline packs, and stream 3 takes
the standard board library which contains descriptions of several
commonly used boards (such as CSD083 and A700).

Defaults: .PIC,DR0:[ESDL]PACKAGES.LIB,DR0:[ESDL]BOARDS.LIB/.BIC,,UNWIRE.LIS

Examples:
\\ \hspace*{ 0.7 in} \} PLACE DEPTLINK
\\ \hspace*{ 0.7 in} \} PLACE MICROCCT,,EUROBOARD.LIB/,MICROCCT.UPD,MICROCCT.UNW

\section{SKETCH}
Sketch takes a placed circuit description and plots the chip
positions as seen from either (or both) sides of the board.
The user is prompted for the device code (HP plotter is 7221,
Charles is 99, Tektronix 4014 is 4014 etc), whether edge
connections should be simple dots or annotated crosses, which
circuit nets should be omitted (end the list with a *) and
which side of the board should be drawn. One the wire side,
the nets can all be drawn, or they can be drawn one at a
time.

Defaults: .BIC

Examples:

\hspace*{ 0.7 in} \} SKETCH MYBOARD

\section{ZAP}
The ZAP program is used to automatically choose sensible
orderings for the nets for Zapping. The user is prompted
for left or right handedness. Note that the default output
overwrites the input so that care is required if the program
is interrupted. Nets of 5 terminals or less are the minimum
length net, larger nets are heuristically routed and nets of
over 25 terminals are not attempted. The ordering will
not survive a DCODE-ESDL cycle.

Defaults: .BIC/$<$root$>$.BIC

Examples:

\hspace*{ 0.7 in} \} ZAP BOARD
\\ \hspace*{ 0.7 in} \} ZAP TEST/TESTZ

\section{VZAP}
The VZAP program is used to interactively amend the ordering
of nets for Zapping. The program runs on either of the
Charles terminals. The mouse is used to reorder the points:

\hspace*{ 0.3 in} White button: reject route
\\ \hspace*{ 0.3 in} Blue button: \hspace{ 0.2 in} accept compete route
\\ \hspace*{ 0.3 in} Yellow button: join to point nearest mouse
\\ \hspace*{ 0.3 in} Green button: join to point nearest last point
\\ \hspace*{ 0.3 in} Green+Yellow: join up rest of route on nearest neighbour

The user is prompted for the threshold below which nets are
assumed to be reasonably routed (see ZAP). The ordering will
not survive a DCODE-ESDL cycle.

Defaults: .BIC/$<$root$>$.BIC

Examples:

\hspace*{ 0.7 in} \} VZAP BOARD
\\ \hspace*{ 0.7 in} \} VZAP TESTZ/TESTZZ

\section{ZLIST}
The ZLIST command is used to produce a listing for production
of a completed design. Inventories of chips and packages,
routing of nets and various indexes are produced.

Defaults: .BIC/$<$root$>$.LIS

Examples:

\hspace*{ 0.7 in} \} ZLIST BOARD
\\ \hspace*{ 0.7 in} \} ZLIST TESTZZ/LISTING

\section{SIM}
The SIM command is used to invoke the gate level simulator.
Commands to drive the simulator are read from the terminal, and
can also be read from input stream 2. An event-trace is produced
on output stream 1, and this can be converted to a signal trace
by use of the POSTPRO command. The circuit definition is read
from input stream 1 and must be a fully flattened, compiled ESDL
description containing only AND, OR, NOT, INV, NAND, NOR,
WAND, WOR, XOR, and NXOR gates. Further HELP information
can be obtained from the simulator itself by issuing the
HELP subcommand.

Defaults: .FIC,.CMD,DR0:[ESDL]SIMULATOR.PRM/$<$root$>$.TRC

Examples:

\hspace*{ 0.7 in} \} SIM JCOUNT
\\ \hspace*{ 0.7 in} \} SIM CIRCUIT,COMMANDS/TRACE
\\ \hspace*{ 0.7 in} \} SIM JKMS.EIC,[XYZ]STDCOMMS

\section{SHOWBOARD}

SHOWBOARD Board,Packlib

Sorry, no Help about this yet

\section{PRESKETCH}
Sorry, no Help about this yet

\section{POSTPRO}
Use the POSTPRO command to produce signal traces from the event-
trace output of the gate-level simulator (see SIM command).
Events are read from input stream 1 and signal traces are produced
on output stream 1 in a form suitable for listing on a character
device such as a line printer. POSTPRO prompts for all the
information it requires, and further help information may be
obtained by replying '?' to these prompts.

Defaults: .TRC/$<$root$>$.WVM

Examples:

\hspace*{ 0.7 in} \} POSTPRO JKMS
\\ \hspace*{ 0.7 in} \} POSTPRO DESIGN/TRACE

\vspace{.75in} view:esdl printed on 15/02/89 at 21.04

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