**********************
* DUART Declarations *
**********************

* Addresses
         org     $01000

base     equ     $10001

vector   equ     30
modea    equ     base+0
stata    equ     base+2
clka     equ     base+2
cmda     equ     base+4
rbaa     equ     base+6
tbaa     equ     base+6
ipcr     equ     base+8
acr      equ     base+8
isr      equ     base+10
imr      equ     base+10
counth   equ     base+12
countl   equ     base+14
modeb    equ     base+16
statb    equ     base+18
clkb     equ     base+18
cmdb     equ     base+20
rbab     equ     base+22
tbab     equ     base+22
ivr      equ     base+24
ipu      equ     base+26
opcr     equ     base+26
srtcnt   equ     base+28
stpcnt   equ     base+30
bitset   equ     base+28
bitres   equ     base+30

* Mode Register 1 (1 command from each group only)

rxrts    equ     $80
norrts   equ     $0

rirdy    equ     $0
rifful   equ     $40

cerr     equ     $0
berr     equ     $20

wthpar   equ     $0
forcep   equ     $8
nopar    equ     $10
multi    equ     $18

evenp    equ     $0
oddp     equ     $4
mdata    equ     $0
maddr    equ     $4

bits5    equ     $0
bits6    equ     $1
bits7    equ     $2
bits8    equ     $3

* Mode Register 2 (1 command from each group only)

norop    equ     $0
echo     equ     $40
lloop    equ     $80
rloop    equ     $c0

txrts    equ     $20
notrts   equ     $0

cts      equ     $10
nocts    equ     $0

stop1    equ     $7
stop2    equ     $f

* Clock select register - Tx and Rx same rates
* (Ba uses SET1 ACR, Bb uses SET2 ACR, B either)

ba50     equ     $0
bb75     equ     $0
b110     equ     $11
b134     equ     $22
bb150    equ     $33
ba200    equ     $33
b300     equ     $44
b600     equ     $55
b1200    equ     $66
ba1050   equ     $77
bb1800   equ     $aa
bb2000   equ     $77
b2400    equ     $88
b4800    equ     $99
ba7200   equ     $aa
b9600    equ     $bb
bb19k    equ     $cc
ba38k    equ     $cc
btimer   equ     $dd
bip16x   equ     $ee
bip1x    equ     $ff

* Command register commands (1 from each group)

* Miscellaneous

nocmd    equ     $0
point1   equ     $10
rstrx    equ     $20
rsttx    equ     $30
rsterr   equ     $40
rstint   equ     $50
brkon    equ     $60
brkoff   equ     $70

* Transmitter

tnoop    equ     $0
ten      equ     $4
tdis     equ     $8

* Receiver

rnoop    equ     $0
ren      equ     $1
rdis     equ     $2

* Output port configuration register

btxrdy   equ     $80
atxrdy   equ     $40
brxint   equ     $20
arxint   equ     $10
ctout    equ     $4
txcb     equ     $8
rxcb     equ     $c
txca16   equ     $1
txca     equ     $2
rxca     equ     $3
allout   equ     $0

* Auxiliary control register (1 from each group)

set1     equ     $0
set2     equ     $80

cntip2   equ     $0
cnttxa   equ     $10
cnttxb   equ     $20
cntxtl   equ     $30
tmrip2   equ     $40
tmrp2    equ     $50
tmrxtl   equ     $60
tmrxxx   equ     $70

* (use 0 to 4 of these- also set inchng in IMR)

delip3   equ     $8
delip2   equ     $4
delip1   equ     $2
delip0   equ     $1

* Interrupt mask register/interrupt status register

inchng   equ     $80
binchng  equ     $7
deltab   equ     $40
bdeltab  equ     $6
irxb     equ     $20
birxb    equ     $5
itxb     equ     $10
bitxb    equ     $4
icntr    equ     $8
bicntr   equ     $3
deltaa   equ     $4
bdeltaa  equ     $2
irxa     equ     $2
birxa    equ     $1
itxa     equ     $1
bitxa    equ     $0
noints   equ     $0

* Status register bits

break    equ     $80
frame    equ     $40
parity   equ     $20
overrun  equ     $10
txempty  equ     $8
txready  equ     $4
ffull    equ     $2
rxready  equ     $1

* Input port change register

delta3   equ     $80
delta2   equ     $40
delta1   equ     $20
delta0   equ     $10
level3   equ     $8
level2   equ     $4
level1   equ     $2
level0   equ     $1

*
start:move.l    #$70000,a0
      move.w    #$ffff,(a0)

* :*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*
*
* INITIALISATION code
*
* :*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*:*
*
* 68681 initialization : 9600 baud,7 data bits, space parity,1 stop bit,
* no parity check
*

	move.l	#table,a0   * get init parameters
	move.l	#length,d0  * get number of parameters
*
	bra sk0init        * do loop test
lp0init:	move.l (a0)+,a1   * get register address
	move.l (a0)+,d1     * parity etc.
*
	move.b	d1,(a1)   	* put command
sk0init:	dbra	d0,lp0init * loop test
*
	move.b	#noints,imr	* clear all interrupt enables
*
*
*
     move.b    #ten,cmda
     move.b    #ten,cmdb
*     move.b    #ren,cmda
*     move.b    #ren,cmdb
     bra       con
*
* set mode of channel A - 7 bits, no parity, 1 stop bit 9600 baud
*  no hsking
*
table:dc.l   imr,noints
     dc.l   cmda,point1
     dc.l   modea,norrts+rirdy+cerr+nopar+bits8
     dc.l   modea,norop+notrts+nocts+stop1
*
* Set mode of Channel B - 7 bits, no parity, 1 stop bit, 9600 baud
* no hsking
*
     dc.l   cmdb,point1
     dc.l   modeb,norrts+rirdy+cerr+nopar+bits8
     dc.l   modeb,norop+notrts+nocts+stop1
*
* set output port config register
*
     dc.l   opcr,allout
*
* Reset and enable channel A
*
     dc.l    cmda,rstrx
     dc.l    cmda,rsttx_* reset transmitter
     dc.l    cmda,rsterr
     dc.l    cmda,rstint
     dc.l    cmda,brkoff+tdis+rdis
     dc.l    clka,b9600
*
* Reset and enable channel b
*
     dc.l   cmdb,rstrx
     dc.l   cmdb,rsttx
     dc.l   cmdb,rsterr
     dc.l   cmdb,rstint
     dc.l   cmdb,brkoff+tdis+ren
     dc.l   clkb,b9600
*
* Setup output pins
*
     dc.l   acr,tmrxxx
     dc.l   bitset,$ff
length equ   (*-table)/8


con:  move.l    #$20000,a1
      move.b    stata,d0
      move.w    d0,(a1)+
     btst.b    #2,stata
     beq       gone     
     move.l    #$70000,a0     * get  led/gen purpose register address
     move.w    #$fffe,(a0)    * put  green led on only.
gone:move.b    #rsterr,cmda
     move.b    stata,d0
     move.b    #ten,cmda
     move.b    stata,d0
go1: bra       go1 
bserr:bra      bserr
aderr:bra      aderr

     org       $0
     dc.l      $2ff00
     dc.l      start
     dc.l      bserr
     dc.l      aderr
*
	end