\documentstyle[12pt,A4]{article}
\title{University Of Edinburgh\\Department of Electrical Engineering\\
       The GATEWAY DESIGN Exercise\\ Manufacturing Release}
\author{ Vinod E.F. REBELLO \\ CS \& E 3}
\date{20th May 1988}
\begin{document}
\pagestyle{headings}
\setlength{\parskip}{0.5cm}
\maketitle
\newpage
\tableofcontents
\newpage
\listoffigures
\newpage
\listoftables
\newpage

\section{Introduction}

This document is the Manufacturing Release for the Gateway Project. The project 
dedicated to committing part of the terminal series' logic
circuitry to ULA. Figure 1 shows the function which has been realised on to an ED500
ULA device.

This device will monitor the screen data bus to indicate whether or not a data value 
on the bus lies within the limits of the screen, and therefore whether or not it 
should be plotted. If a set of data values on the bus represent a point not on the 
screen display, attempting to plot them only results in wasted time. 

The ULA device produces three outputs :

\begin{itemize}
\item
 PLOT - indicates whether the datum is within the screen limits.

\item 
 GT   - indicates that the datum is greater than the upper screen limit.

\item
 LT   - indicates that the datum is less than the lower screen limit.
\end{itemize}

Only one of these outputs can be asserted at any one time.

\begin{figure}[htb]
\vspace{12cm}
\caption{ The Gateway Circuit Assignment.}
\end{figure}


The X/Y data represent either the x or y coordinate of the pixel to be illuminated,
and the x0/y0 data are the corresponding offsets (i.e. the actual pixel illuminated
will have coordinates ( x0 + x, y0 + y ). The ULA can be permanantly configured
as either an 'X' or 'Y' model.

Limits which correspond to the screen limits have been coded onto the chip and are 
not inputs from outside. Since the same basic ULA design is to be usable as both
'X' and 'Y' data monitors, the limits are mask programmable and thus easily 
changeable, as the screen is not square.

This design complies with the 2 main constraints set out in the Design Specification
 :
\begin{itemize}
\item
 The device does have an input-output delay of less than 4$\mu$S to allow for the
assumed data rate of 125 KHz.

\item
 The size of the function does not exceed the 60 ULA cell limit.
\end{itemize}


\clearpage

\newpage
\section{Logic Design}
\subsection{ Introduction}
 From Figure 1, It can be seen that there are two main operations the functions
needs to carry out.
\begin{itemize}
\item
 The Data and Offset values need to be added together. An ADDER.

\item
 The result of the addition then needs to be compared with the upper and lower
limits of the screen. Two COMPARATORS.
\end{itemize}

\begin{figure}[htb]
\vspace{8cm}
\caption{ Block diagram of the Required ULA Function.}
\end{figure}

For an indepth analysis and derivation of the Logic
 Design refer to the Definition 
Release ( December 1987 ).

\subsection{ The ED500 ULA Cell}
The cell of the ED500 ULA device, Figure 4, contains a total of four MOS
transistors. M1, M2 and M3 are enhancement mode MOS transistors and M4 is a depletion
mode transistor. Transistor M3 and M4 are permenantly connected as an inverter. 


\begin{figure}[htb]
\vspace{13cm}
\caption{The Gateway Array Cell Layout}
\end{figure}

However the cell can be configured in many ways to perform a range of logic functions
( 2/3 input NOR's, 2 input NAND's, NOR(AND) and NAND(OR)).

\clearpage

In order to produce a compact high quality design without complex routing, we
 minimised the number of cells 
required for the whole function by aiming to derive
expressions of the form using those types of gates. Although there three 
enhancement transistors allowing gates with three inputs, we cannot have a three
input NAND gate due to conflict with MOS transistor design constraints.
Figure 4. also shows schematically some predefined interconnections or
underpasses within the cell.

\subsection{ The Four Bit Chained Adder}
\subsubsection{ A Closer Look at the Adder}
A four bit adder can be broken into four blocks. Each blocks adds the
corresponding bits plus the previous carry and outputs a sum and a carry signal.
( This block is called a full adder). 

\begin{figure}[htb]
\vspace{8cm}
\caption{Block Diagram of Inputs and Outputs for a Full Adder}
\end{figure}

The addition of two four bit numbers will give a 5 bit result. From the initial 
design specification we are only required to feed the top four bits to the 
comparators i.e. the top carry bit and the top three sum bits.
This means we don't need the sum of the least significant bits of the data and offset,
just the carry.

The bottom Half adder block can be simplified as shown in Figures 5 and 6. 

\begin{figure}[htb]
\vspace{12cm}
\caption{ Block diagram of a Four Bit Adder.}
\end{figure}
\clearpage

\subsubsection{The Adder Logic Circuit}
With the help of truth tables and the use of Karnaugh maps we can simplify the 
expressions and thus derive the required logic for each of the blocks and therefore 
build up the circuit for the adder.

The logic circuit for $C_{4}$ is trivial since

\begin{equation}
C_{4} = D_{4}.O_{4}
\end{equation}

requires only an AND gate. However only NAND gates are available and therefore
we require an additional inverter. This takes up two ULA cells in total.

\begin{figure}[htb]
\vspace{4cm}
\caption{ Logic Circuit for a Half Adder}
\end{figure}

We can simplify $S_{n}$ and $C_{n}$ to produce a minimum cell count with out
 serious routing problems

\begin{equation}
S_{n} = ( D_{n} \oplus O_{n} ) \oplus C_{n-1} 
\end{equation}

( $\oplus$ is an EXOR gate which can be realised  in two cells as

\begin{equation}
A \oplus B = \overline{\overline{A + B} + A.B}
\end{equation}

In order to minimse the number of gates used we aimed to simplify one function in
relation to one we have already simplified.

\begin{eqnarray}
C_{n} = \overline{\overline{D_{n} + O_{n}} + \overline{D_{n}.O_{n} + C_{n-1}}}
\\
 \overline{D_{n} + O_{n}}\  is\  part\  of\  the\  EXOR\  function.\    \nonumber
\end {eqnarray}

The circuit diagram for the full adder becomes :

\begin{figure}[htb]
\vspace{8cm}
\caption{ Logic Circuit for the Full Adder Block}
\end{figure}

\begin{eqnarray*}
No. of cells &=& ( 3 X full adder cells ) + half adder cells\\
             &=& ( 3 X 6 ) + 2\\
             &=& 20 cells.\\
\end{eqnarray*}
\clearpage

\subsection{ The Comparators}
\subsubsection{ Approach }
In order to do a comparision each bit of the sum will be compared with the
corresponding bit of the limit.
In order to reduce the amount of work that needs to be done we can say that if the
most significant ( M.S.) bit of the sum is grater than the corresponding M.S. bit
of the limit then the sum is greater than the limit. Similarily if the M.S. bit of
the sum was less than the M.S. bit of the limit, the sumwould be less than the limit.
If however the bits are equal we must look at the next most significant bits and
 compare as before.


\subsubsection{ A General One Bit Comparator}
Since the limit will be masked on we developed the following cell which compares
the sum bit with the limit ( which cam be '0' or '1' ).

\begin{figure}[htb]
\vspace{7cm}
\caption{ 1 bit Comparator : Mask on the value of limit ( 0/1) 
to which S is being compared.}
\end{figure}
\clearpage

The will outputs a greater and a less than signal. Both will not be asserted at the
same time, however both may be low indicating that the two bits are equal.

\subsubsection{ The Greater and Less Than Comparators}
We need Four of the 1 bit comparator cells to make a four bit comparison. We  also
need further logic to compare the results from all the bit comparators
i.e. if the significant bit comparision returs 'equivalent' we need the result of
the next most significant comparision.

\begin{figure}[htb]
\vspace{8 cm}
\caption{ Block Diagram of Addtional Comparator Logic.}
\end{figure}

C is the Greater than signal in the 'GT' comparator. $C_{G}$


C is the Less than signal in the 'LT' comparator. $C_{L}$


Again using truth tables and Karnaugh maps we obtained :
\begin{eqnarray}
C_{G} & = & \overline{L + \overline{G + C_{*}}}\\
C_{L} & = & \overline{G + \overline{L + C_{*}}}
\end{eqnarray}
The equation for the lowest block is even simpler since there is no previous
chained signal :
\begin{eqnarray}
C_{G} & = & G\\
C_{L} & = & L
\end{eqnarray}

The full logic for the two comparators is very similar.

\begin{figure}[htb]
\vspace{17cm}
\caption{ Logic Circuit for the Greater Than and Less than Comparators}
\end{figure}

Each comparator takes up 20 ULA cells.
\clearpage

\newpage
\section{The Limits' Programmablity}

In a one bit comparator we program the limit value by the corrsponding connections
at the metallisation level i.e. the last masking stage.

\begin{figure}[htb]
\vspace{22cm}
\caption{ Setting the One Bit comparator}
\end{figure}

0 - 15 can be represented in binary as a 4 bit number $A_4A_3A_2A_1$
where $A_n$ can be 0 or 1.
For this prototype :

\begin{eqnarray*}
upper limit & = & 13_{10} \\
            & = & 1101_{2}\\
lower limit & = & 11_{10}\\
            & = & 1011_{2}\\
\end{eqnarray*}

Now by simply setting each of the one bit comparator,s ( as in Figure 11 ),
to the corresponding bit that 
they represent, by making the correct mask connections as above. The required limits
are thus incorporated into the design.

These values can be changed by resetting the each of the bit comparators. This of
course involves an amendment to the metallisation mask.


See Appendix A to set the bit comparator at a metal mask level.

\clearpage
\newpage
\section{Feasibility}
\subsection{Gate Array Layout}
The placing of the logic gates in cells and final arrangements of the Adder and 
comparators are shown in figure  .

The total number of cells is 86, however only 41 cells are used for logic
gates. The other 45 are just used to route metal through. Hence the design
is within the 60 ULA cell limit.

\begin{figure}[htb]
\vspace{22cm}
\caption{ ULA layout of Adder and Comparators}
\end{figure}
\clearpage

\subsection{Gate Array Performance}
The overall emphasis is to explore the problems of logic design and interconnection.
However, it is essential to consider functional and electrical performance in the 
design. The gate Array ED500 cell output has speed characteristics which depends
on the capactive loading of the output node such that
 the rise time of the node is
\begin{equation}
TR( nS ) = 500 X C( pF )
\end{equation}
Similarly the fall time is 
\begin{equation}
TF( nS ) = 500 X C( pF )
\end{equation}
Here the time is in Nano Seconds and the capacitance in Pico Farads.
\begin{table}[htb]
\begin{center}
\begin{tabular}{|l|c|}\hline
FEATURE & CAPACITANCE\\\hline \hline
metallisation & 0.0006 pF/grid \\
Gate Inputs & 0.02 pF \\
Inter--cell Cross Unders & 0.1 pF each\\
Within--cell Cross Unders & 0.05 pF each\\\hline
\end{tabular}
\end{center}
\caption{Interconnection Capacitance Values}
\end{table}
The input to output propagation delay can now be calculated using equations...
and the above table. 

The maximum delay will occur if we assume that all the gate output logic levels
along the critical capacitance path will be rising. This in practice will never
 occur with
such logic gates since some values will be rising while others falling.
This delay will be an over estimation of the worst possible delay. This allows
some margin for stray capacitance offboard and for electrical/array characteristical
faults which may develope during manufacture.

Another method of obtaining a more accurate value other than actually measuring it
is to find out which gate logic values are rising and which are falling. This is
difficult to do with out using some computer software as it is possible that the
worst time delay may not lie along the critical capacitance path.

Figure 13 shows the logic circuit with load capacitance written in black beside
each gate. The Critical Path capacitance ( marked in red ) being the longest
capacitance path through the circuit. If we sum the capacitances between the gates
on the critcal path ( these values include fanout ) and apply equation ..
One also  remember that since only one of the outputs may be high for a valid 
answer and therefore since Critcal path is on the 'LT' signal we must add the
fall time on the 'PLOT' signal to allow for valid output.

\begin{figure}[htb]
\vspace{22cm}
\caption{ The Logic Circuit showing Gate Load Capacitances.}
\end{figure}

\begin{eqnarray*}
propagation\  delay & = & Rise\  time\  of\  Critical\  Path\  + \  \\
 & & Fall\  time\  of\  'PLOT'\  output \\
 & = & 500 \times C_{cp} + 50 \times C_{plot}\\
 & = & 500 \times 4.54 + 50 \times 1.022\\
 & = & 2.321 nS  < 4nS\\
\end{eqnarray*}

\clearpage

\newpage
\section{Testing}
\subsection{ Pre Fabrication Testing}
In order to improve the chances of producing correctly functioning devices and
save both money and time at later stages in developement, as with current 
practice, the design was placed the departmental PCAD facility.

This means that the design can be changed or updated easily and also allow 
a software based simulator to test the design such as GSIM on a VAX computer.
The design was  rigorously tested and checked so that the outputs
were correct for all given inputs.

\input{gate2}
\subsection{Post Fabrication Testing}
 The use of Logic Analysers and a DAS enable accurate timings of propagation
delays, rise and fall times to calulated. They allow investigation of the
electrical characteristics of the circuit and hopefully identify any flaws in
design and fabrication.

\newpage
\section{Project Management}
\subsection{Hours Spent}
The following major tasks where necessary to complete this project.
\begin{itemize}
\item
Pre Project Planning\\
This involved an indepth analysis of what was entailed by the project.
\item
Partitioning\\
How the problem was to be split up and the maximum time to spent on each task.
\item
Design ( Discrete Logic ) \\
Having the design on paper in logic gates.
\item
Design ( ULA Mapping )\\
Converting the logic gates into metalisation masks and mapping the whole circuit
on to the array.
\item
PCAD and Simulation\\
Placing the design on the Pcad facility and Simulating the design.
\item
Documentation\\
Writing both Definition and Manufacturing Releases.
\end{itemize}

\begin{table}[htb]
\begin{center}
\begin{tabular}{|l|c|}\hline
TASK & HOURS SPENT\\ \hline \hline
Pre Project Planning & 2 \\
Partitioning & 2 \\
Design ( Discrete Gates ) & 16\\
Design ( ULA Mapping) & 3\\
PCAD and Simulation & 6\\
Documentation & 12\\ \hline
TOTAL & 41 \\\hline
\end{tabular}
\end{center}
\caption{ Hours Spent on each Task}
\end{table}

\subsection{Costing}
\begin{eqnarray*}
Project\  Budget &=& \pounds 5000 \\
& & \\
100\  devices\  required\  @\  \pounds 20 &=& \pounds 2000 \\
Mask\  Making\  ( by\  Compugraphic ) &=& \pounds 2000 \\
41\  hours\  @\  \pounds 125\  per\  7\  hr\  charge\  rate &=& \pounds 732 \\
Total\  Project\ Cost &=& \pounds 4732 \\
\end{eqnarray*}

The project was thus \pounds 268 within Budget.

\newpage
\section{Improvements}
It is still possible to yet improve on the characteristics of the circuitry.
\subsection{Layout}
The Adder is as small as can be without seriously causing major routing problems.
It could however be reduced by one ULA cell.

The Comparators however could be reduced by 5 - 6 ULA cells by redesigning the bit
comparator and the first gate if necessary.

\subsection{Timing}
With improvements in the layout design of the comparators an improvement does seem
possible. But eventually some thought will be required to speed up the adder as
well.

Other solution is to use a smaller array size since the circuit does utilise only
half to a quarter the current number of cells.

If after this circuit optimisation the delay is still too long, the use of some
type of technology other than NMOS 6$\mu$m should be used. Such as TTL ( LS, S, 
ALS or FAST ) or for faster circuitry CMOS could be used, both of which are
cheap and readily available.

\newpage
\section{Conclusions}
It has been shown that this Application Specific Ingrated Chip ASIC device
complies to the constraints set out in the initial specification. Its limits 
are easily programmable and the Project was completed within the allocated budget.
\newpage
\section{Appendix A}
\begin{figure}[htb]
\vspace{22cm}
\caption{Logic Gates Used in the Design. (1)}
\end{figure}
\begin{figure}[htb]
\vspace{22cm}
\caption{Logic Gates Used in the Design. (2)}
\end{figure}
\begin{figure}[htb]
\vspace{22cm}
\caption{Setting the 1 Bit Comparator.}
\end{figure}
\clearpage
\newpage
\section{Appendix B}
\newpage
\begin{figure}[htb]
\vspace{22cm}
\caption{ULA Mask for the Logic Function}
\end{figure}
\clearpage
\section{Appendix C}
\newpage
\begin{figure}[htb]
\vspace{12cm}
\caption{Project Planning Sheet.}
\end{figure}
\end{document}
