liston
$ MSF clock board decoder
$ David A Kerr 1985     CS&E4 Honours project
$ Following is the ESDL source for the MSF clock decoder board
$ on EuroZap2G board. Use the following library files:
$ this is...  MSF.SRC
$ packages..  MSFP.SRC
$ chips.....  MSFC.SRC
$ board.....  MSFB.SRC

unit MSF_Clock(

$ APM Bus Connector
$ back bus of the EUCSD APM system

.gnd,.gnd,.gnd,
.gnd,.gnd,.gnd,
.vp12,.vp12,.vp12,
.vm12,.vm12,.vm12,
apmad'<2:31>,
apmco'<0:3>,
apmreserved,apmr\w',
apmbrq',apmcbr',apmbgr',
apmrst',apmmclk,apmpfl',
apmtac',apmatm',apmtrq',
apmerr',
apmda<30:37,20:27,10:17,0:7>,
.vm5,.vm5,.vm5,
.vcc,.vcc,.vcc)
pins (
a01a,a01b,a01c,a02a,a02b,a02c,
a03a,a03b,a03c,a04a,a04b,a04c,
a05a,a05b,a05c,a06a,a06b,a06c,
a07a,a07b,a07c,a08a,a08b,a08c,
a09a,a09b,a09c,a10a,a10b,a10c,
a11a,a11b,a11c,a12a,a12b,a12c,
a13a,a13b,a13c,a14a,a14b,a14c,
a15a,a15b,a15c,a16a,a16b,a16c,
a17a,a17b,a17c,a18a,a18b,a18c,
a19a,a19b,a19c,a20a,a20b,a20c,
a21a,a21b,a21c,a22a,a22b,a22c,
a23a,a23b,a23c,a24a,a24b,a24c,
a25a,a25b,a25c,a26a,a26b,a26c,
a27a,a27b,a27c,a28a,a28b,a28c,
a29a,a29b,a29c,a30a,a30b,a30c,
a31a,a31b,a31c,a32a,a32b,a32c)

on eurozap2g

$ circuit diagram page 1

$ data strobe validity decoding
$ the MSF board MUST be accessed in BYTE mode only, the attempt
$ to address it as Word or Long Word is not permitted.
$ following discrete logic determines that this is so.
$ 1) buffer the apm CO0L, CO1L, CO2L, CO3L lines through ls240 chip
$ 2) discrete logic to test for one and only one line asserted
$ 3) final output (active high) asserted as 'dataok'
$ 'ad0l' and 'ad1l' are derived for the lowest two bits of address.
u240(apmco'<0:3>,low) -> dst<0:3>
nor(dst<1>,dst<3>) -> ad0l
nor(dst<0>,dst<1>) -> vd1
xor(dst<2>,dst<3>) -> vd2
nor(dst<2>,dst<3>) -> ad1l
xor(dst<0>,dst<1>) -> vd4
nand(vd1,vd2) -> vd5
nand(ad1l,vd4) -> vd6
nand(vd5,vd6) -> dataok

$ having determined that the addressing mode is BYTE,
$ combine the 'dataok' signal with the bus acknowledge
$ signal from the Z80 to enable the transfer.
$ 'entrans' then enables the appropriate tristate buffer
$ for the BYTE transfer.
$ 'aen' is derived to enable the apm address lines onto
$ the local Z80 bus.
inv(zbusak) -> busok
and(busok,dataok) -> entrans
nand(entrans,dst<0>) -> den<0>
nand(entrans,dst<1>) -> den<1>
nand(entrans,dst<2>) -> den<2>
nand(entrans,dst<3>) -> den<3>
inv(entrans) -> aen

$ the apm TRQL and R\WL lines are tristate buffered
$ onto the local Z80 bus equivilents 'zmreq' and 'zwe'
$ buffer the TRQL and R\WL onto Z80 equivilents
$ the data direction control 'ddc' is gated with the transfer
$ acknowledge signal 'tacl' to ensure negation and thus latching
$ of data on a write cycle.
u125(apmtrq',low) -> adec
u125(apmr\w',low) -> ddc
u125(adec,aen) -> zmreq
inv(tacl) -> tl'
or(tl',ddc) -> wen
u125(wen,aen) -> zwe

$ the transfer acknowledge circuit is based on two flip flops
$ which acknowledge tha transfer after a guaranteed mimimum and
$ maximum period.
$ 1) Z80 bus request and bus acknowledge signals are gated together
$    to indicate that the Z80 is permitting the transfer, 'dtac'.
$ 2) this is gated with the apm transfer request/address decode
$    line to enable the acknowledge cycle 'dack'.
$ 3) the 'dataok' signal is enabled onto the 'error' line and open
$    collector buffered onto the apm ERRL line if board was not addressed
$    in BYTE mode.
$ 4) the two flip flops are clocked on 3.2768 Mhz and inverse. The
$    two outputs are geted onto TACL and open collector buffered to apm
or(zbusak,zbusrq) -> dtac
or(dtac,adec) -> dack
or(dataok,dack) -> error
bufoc(error) -> apmerr'
inv(clock) -> ckinv
u74(dack,phff1,phff1,clock) -> dq1,empty3o
u74(dack,phff1,phff1,ckinv) -> dq2,empty4o
or(dq1,dq2) -> tacl
bufoc(tacl) -> apmtac'

$ the clock and interrupt timing circuit.
$ base clock frequency is 3.2768 Mhz, this drives the local 'clock' line
$ and the Z80. A 200Hz (5mS) frequency is derived from this and clocks
$ a flip flop. This drives the Z80 interrupt line 'zint' which in this
$ simple hardware configuration is acknowledged by the Z80 I/O request
$ line 'zioreq'.
Xtal -> clock
cd4020(clock,low) -> empty5o<0>,empty5o<3:12>,divck
u74(phff2,phff2,zioreq,divck) -> empty6o,zint


$ circuit diagram page 2
$ tristate bidirectional buffering of data lines
$ the 32 bit apm data bus is divided into 4 byte blocks, only one
$ of which is enabled at any one time. Tristate bi-directional
$ buffering enabled by the data enable 'den<?>' signal links this
$ to the Z80 data bus
u245(ddc,den<0>,zd<0:7>) -> apmda<0:7>
u245(ddc,den<1>,zd<0:7>) -> apmda<10:17>
u245(ddc,den<2>,zd<0:7>) -> apmda<20:27>
u245(ddc,den<3>,zd<0:7>) -> apmda<30:37>

$ circuit diagram page 3
$ tristate buffering of address bus
$ lower 16 bits of apm address bus is tristate buffered onto the
$ Z80 address line. Lowest two lines are derived above. The
$ buffers are enabled by the address enable signal 'aen'.
u240(apmad'<12:15>,aen) -> za<12:15>
u240(apmad'<8:11>,aen) -> za<8:11>
u240(apmad'<4:7>,aen) -> za<4:7>
u240(ad0l,ad1l,apmad'<2:3>,aen) -> za<0:3>

$ decoding of upper 16 address lines on bus
$ the MSF clock board is selected when the upper 16 addres
$ lines equal the values selected by the rotary binary switches.
$ ls521's are used to compare the two addresses and an
$ open collector driver drives an LED indicator. Resistor
$ pacs pull the default address to high.
u521(apmad'<16:23>,adsel<16:23>,adec) -> lowerok
u521(apmad'<24:31>,adsel<24:31>,lowerok) -> zbusrq
bufoc(zbusrq) -> led2
led(high) -> led2
binswitch(low) -> adsel<16:19> at ni0
binswitch(low) -> adsel<20:23> at ni1
binswitch(low) -> adsel<24:27> at ni2
binswitch(low) -> adsel<28:31> at ni3
respac1k(adsel<16:23>) -> high
respac1k(adsel<24:31>) -> high

$ circuit diagram page 4
$ the seven segment led display driver etc
$ a 74C917 is a specialized led display driver, it is connected
$ direct to the Z80 bus
$ the seven segments + point are driven through 8 resistors
$ and each digit multiplexed through 6 transistors hand mounted
$ on a DIL header.
u917 (zd<0:4>,za<0:2>,md<6>,zwe,low,low) -> dis<1:6>,seg<1:8>
respac330(seg<1:8>) -> ledseg<1:8>
trans(dis<1:6>) -> leddis<1:6>
dilled(leddis<1:4>,ledseg<1:8>)                 at a30
dilled(leddis<5:6>,empty7i,empty8i,ledseg<1:8>) at a22

$ the I/O bits
$ 4 input bits are buffered onto the Z80 data lines for the
$ MSF signal and dil switches.
or(zre,md<7>) -> ioen
u240(io<0:3>,ioen) -> zd<0:3>
dilsw4(low,low,low,low) -> pfen,io<1:3>

$ power fail to NMI and reset to RESET
$ the apm power fail signal is tied to the Z80 nmi signal through
$ a disabling gate, tied to one of the DIL switches.
$ the apm reset line is similarly tied to the Z80 reset.
or(apmpfl',pfen) -> znmi
nor(apmrst',io<1>) -> rst1
$ tie in with power up reset circuit
invs(pupres) -> rst2
nor(rst1,rst2) -> zreset

$ the input from Rx
$ the MSF input signal is tied into the Z80 buffered input lines and
$ also drives an LED indicator
$ *** WHEN CONSTRUCTING ADD A 330R RESISTOR TO LED LINE IF THE LED
$ *** CANNOT BE DRIVEN DIRECTLY FROM 5 VOLTS.
bufoc(io<0>) -> led1
invs(pulsein) -> io<0>
led(high) -> led1
plugin(rxvcc,rxdata,low)

$ discrete components
$ all mounted on the one dil 16 pac
H1(rxv1) -> rxvcc
C1(rxv1) -> low
R1(rxv1) -> high

H2(pulsein) -> rxdata
C2(pulsein) -> low

R2(pupres) -> high
D1(pupres) -> high
C3(pupres) -> low

$ circuit diagram page 5
$ the memory bank and the memory select logic
$ originaly 6 sockets selectable between RAM/EPROM (6116, 2716)
$ was provided. In practice two is all that is required so others
$ commented out.
u138(za<13:11>,ph138,low,zmreq) -> md<7:0>
u6116(za<10:0>,md0we',md<0>,md<0>) -> zd<7:0> at a66
link(zwe,epromph) -> md0we'                   at b66
u6116(za<10:0>,md1we',md<1>,md<1>) -> zd<7:0> at c66
link(zwe,epromph) -> md1we'                   at d66
u6116(za<10:0>,md2we',md<2>,md<2>) -> zd<7:0> at e66
link(zwe,epromph) -> md2we'                   at f66
$u6116(za<10:0>,md3we',md<3>,md<3>) -> zd<7:0> at h66
$link(zwe,epromph) -> md3we'                   at j66
$u6116(za<10:0>,md4we',md<4>,md<4>) -> zd<7:0> at k66
$link(zwe,epromph) -> md4we'                   at l66
$u6116(za<10:0>,md5we',md<5>,md<5>) -> zd<7:0> at m66
$link(zwe,epromph) -> md5we'                   at n66

$ circuit diagram page 6
$ everything pulled together on the Z80 cpu !!!
uZ80(zd<0:7>,zwait,zint,znmi,zreset,zbusrq,clock)
  -> za<0:15>,zm1,zmreq,zioreq,zre,zwe,zrfsh,zhalt,zbusak

$ everything which has to be pulled high via 1K *13 resistors
drespac1k(pfen,io<1:3>,phff1,phff2,epromph,ph138,zwait,zwe,zre,zioreq,zmreq)
       -> high

end

finish
