\documentstyle[a4,12pt]{article}
\begin{document}
\author{APM Manual pages}
\title{APM Working Documents}
\maketitle
\parskip .1 in
\setcounter{secnumdepth}{10}
\parindent 0in

\section{Preamble}
\hspace*{1.5 in} APM Working Documents

This is a set of notes by Fred King describing portions of the APM
design. It was collected after he left so is a bit disorganised but is
included here for reference.

These files comprise the bulk of the departmental report "APM Working Documents"
\section{Introduction}
Missing

\section{EUCSD BUS}

\subsection{Introduction}

The EUCSD bus is an interconnection system for computer components.
Its design goals were those of simplicity, flexibility and performance.
It was assumed that the components to be connected would fall into three
categories :

1. Memories - accessible from all other devices.

2. Main processors - with no I/O capability.

3. I/O processors - providing I/O facilities for the system.

The two significant features of the system are that there are multiple
processors sharing common resources and that there are no simple I/O
devices connected directly to the bus.

Multiple processors imply that the bus must be shared fairly among them.
To achieve this, a bus controller that gives bus arbitration facilities
must be provided as part of the bus structure. This is implemented
as a central facility that has separate connections to each of the
potential bus masters.

As there are no simple I/O devices on the bus, it is possible to avoid
providing a fixed interrupt structure. These facilities are provided
by control registers associated with processors. When these control
registers are accessed from the bus, the effect
is to cause an interrupt request
to the corresponding processor.
The form and number of these registers are determined by the nature of the
processor with which they are associated.
As only 'intelligent' interrupting devices are attached directly to the
bus, differences between the processors can be handled in software.
As a result, the only transfers on the bus comprise fully addressed
exchanges of data between 'active' masters and 'passive' slaves.

\subsection{Functional Description}


\subsection{Mechanical Details}

All boards are Double height extended depth Eurocards (233.4mm X 220mm).
The Bus is connected by a single DIN41612 C 96 way connector positioned
as in the following diagram :

\small\tt \begin{verbatim}           |----------------- 220 mm ----------------|
     _____  _________________________________________
      |    |                                        _|
      |    |                                       | |
      |    |                                       | |
      |    |                                       | |
      |    |                                       | |    Bus
      |    |                                       | | Connector
      |    |                                       | |
      |    |                                       | |
      |    |                                       | |
      |    |                                       |_|
      |    |                                         |
      |    |                                         |
  233.4 mm |            Component Side.              |
      |    |                                         |
      |    |                                        _|
      |    |                                       | |
      |    |                                       | |
      |    |                                       | |
      |    |                                       | |  Unused
      |    |                                       | | Connector
      |    |                                       | |
      |    |                                       | |
      |    |                                       | |
      |    |                                       |_|
     _|___ |_________________________________________|
\end{verbatim}\rm  \normalsize 
The unused connector position may be used freely to provide off-board
or inter-board connections.
It is intended that this facility should be used to
communicate with other buses and systems.


\subsection{Connector Pin Assignment}

\small\tt \begin{verbatim} pin no          row 
          a       b       c

      1 GND     GND     GND 
      2 GND     GND     GND 
      3 +12V   +12V     +12V 
      4 -12V   -12V     -12V 
      5 AD2L   AD3L     AD4L 
      6 AD5L   AD6L     AD7L 
      7 AD8L   AD9L     AD10L 
      8 AD11L  AD12L    AD13L 
      9 AD14L  AD15L    AD16L 
     10 AD17L  AD18L    AD19L 
     11 AD20L  AD21L    AD22L 
     12 AD23L  AD24L    AD25L 
     13 AD26L  AD27L    AD28L 
     14 AD29L  AD30L    AD31L 
     15 CO0L   CO1L     CO2L 
     16 CO3L   reserved R/WL 
     17 BRQiL  CBRL     BGRiL 
     18 RSTL   MCLK     PFLL 
     19 TACL   ATML     TRQL 
     20 ERRL   DA30L    DA31L 
     21 DA32L  DA33L    DA34L 
     22 DA35L  DA36L    DA37L 
     23 DA20L  DA21L    DA22L 
     24 DA23L  DA24L    DA25L 
     25 DA26L  DA27L    DA10L 
     26 DA11L  DA12L    DA13L 
     27 DA14L  DA15L    DA16L 
     28 DA17L  DA00L    DA01L 
     29 DA02L  DA03L    DA04L 
     30 DA05L  DA06L    DA07L 
     31 -5V    -5V      -5V 
     32 +5V    +5V      +5V 
\end{verbatim}\rm  \normalsize 

\subsection{Signal Descriptions}

\subsubsection{Unused pins}

\hspace*{0.2 in} Pin 16b is unused and reserved. Under NO
\\ \hspace*{0.2 in} circumstance should this pin be used.


\subsubsection{Power supplies}

\small\tt \begin{verbatim} GND     Common signal and supply ground.

+12V     Positive 12 volt supply.

-12V     Negative 12 Volt supply.

 +5V     Positive 5 Volt supply.

 -5V     Negative 5 Volt supply.
\end{verbatim}\rm  \normalsize 

\subsubsection{Bus Signals}

All bus signals are active low TTL level signals. Thus
the Asserted (Ass) state is defined to be $<$=0.8V and the Negated (Neg)
state to be $>$=2.0V.

The signal type specifies whether the signal driver is a TTL totem pole
output (ttl), a TTL open collector output (o/c) or a TTL three state
output (3-s).

The significance of assertion or negation of Address and
Data signals on the bus is not specified as part of the bus protocol.
This will be dermined by mutual aggrement of the
masters and slaves in any given system.
However all simple memory devices MUST present read data in the SAME
state as it was written.
By convention, address selection logic will assume TTL low on the bus
to be binary 1 and TTL high on the bus to be binary 0, with AD2L the least
significant bit and AD31L the most significant bit.
In general, module address recognition logic will not decode more than the
16 most significant address lines.

\small\tt \begin{verbatim}Signal  Type  Driver     Validity   Description

BRQiL   ttl   Masters    always     Bus request from master to arbiter.
                                    Asserted whenever master wishes to
        NOT BUSSED                  use the bus and for the period while
        ----------                  the master has control of the bus.

BGRiL   ttl   Controller always     Bus grant from arbiter to master.
                                    Asserted whenever master has
        NOT BUSSED                  requested and has been granted
        ----------                  use of the bus.


CBRL    o/c   Masters    always     Common bus request. Asserted
                                    whenever a master has requested
                                    but not yet been granted use of
                                    the bus. This indicates to the
                                    current bus master that other
                                    potential masters are requesting
                                    the bus.

RSTL     ttl   Controller Always    System reset. Forces all devices
                                    into a known initial state.

MCLK     ttl   Controller Always    Mains derived 100Hz clock. A train
                                    of 1ms wide low going pulses within
                                    1ms of the zero crossing of the AC
                                    mains.

PFLL     ttl   Controller Always    Mains supply failure. DC supplies
                                    should be stable while this signal
                                    is negated and for at least 5ms
                                    after the assertion of this signal.

ATML    o/c   Masters    always     Asserted by the current master at
                                    the begining of an indivisible bus
                                    transaction. Is negated only when
                                    TRQL is negated on the last transfer
                                    of the transaction. The transaction
                                    may consist of a single bus transfer.

TRQL    o/c   Masters    always     Asserted by the master in control
                                    of the bus when a transfer is
                                    required. This must occur only
                                    after AD2L-AD31L, R/WL, CO0L
                                    and if R/WL is asserted,
                                    DA00L-DA37L are valid and stable.
                                    It is negated only after these
                                    signals are deselected in response
                                    to TACL being asserted.

TACL     o/c   Slaves     Always    Asserted by the slave addressed in
                                    a transfer once the transfer is
                                    complete. This must occur only
                                    after ERRL and if R/WL is negated,
                                    DA00L-DA37L are valid and stable.
                                    It is negated only after these
                                    signals are deselected in response
                                    to TRQL being negated.

               Controller           In the event of no slave asserting
                                    TACL within 2000ns of TRQL being
                                    asserted the controller will assert
                                    both TACL and ERRL to force
                                    unsuccessful termination of the
                                    reqested transfer.

ERRL     o/c   Slaves     TRQL Ass  Slave error response. Asserted if
                          TACL Ass  the slave cannot succesfully
                                    complete the transfer.

               Controller           In the event of no slave asserting
                                    TACL within 2000ns of TRQL being
                                    asserted the controller will assert
                                    both ERRL and TACL to force
                                    unsuccesful termination of the
R/WL     3-s   Masters    TRQL Ass  Read/write line. Determines the
                          TACL Neg  direction of transfer on the bus.
                                    When asserted the direction is from
                                    Master to Slave. When negated is
                                    from Slave to Master.

AD2L -   3-s   Masters    TRQL Ass  Word address signals.
  AD31L                   TACL Neg

CO0L -   3-s   Masters    TRQL Ass  Byte strobes. Determines which
  CO3L                    TACL Neg  data bus bytes are active in a
                                    transfer. Used as follows :
                    If CO0L asserted then DA00L-DA07L are active.
                    If CO1L asserted then DA10L-DA17L are active.
                    If CO2L asserted then DA20L-DA27L are active.
                    If CO3L asserted then DA30L-DA37L are active.
                    Otherwise the corresponding data lines are held in
                    the high impedance state and take no part in the
                    transfer.

DA00L -  3-s   Masters    TRQL Ass   byte 0 data signals.
  DA07L        (R/WL Ass) TACL Neg
                          CO0L Ass

               Slaves     TRQL Ass
               (R/WL Neg) TACL Ass
                          CO0L Ass
                          ERRL Neg

DA10L -  3-s   Masters    TRQL Ass   byte 1 data signals.
  DA17L        (R/WL Ass) TACL Neg
                          CO1L Ass

               Slaves     TRQL Ass
               (R/WL Neg) TACL Ass
                          CO1L Ass
                          ERRL Neg

 DA20L -  3-s  Masters    TRQL Ass   byte 2 data signals.
   DA27L       (R/WL Ass) TACL Neg
                          CO2L Ass

               Slaves     TRQL Ass
               (R/WL Neg) TACL Ass
                          CO2L Ass
                          ERRL Neg

 DA30L -  3-s  Masters    TRQL Ass   byte 3 data signals.
   DA37L       (R/WL Ass) TACL Neg
                          CO3L Ass

               Slaves     TRQL Ass
               (R/WL Neg) TACL Ass
                          CO3L Ass
                          ERRL Neg
\end{verbatim}\rm  \normalsize 


\subsection{Bus Protocol}

A master wishing to perform an exchange of data on the bus must
obey a three level protocol.
The first level deals with acquiring control of the bus.
The next level deals with delimiting bus transactions,
during which no information accessible from the bus can
be altered other than by the current master. This is included
to deal with dual-ported memories which can be changed by
sources other than the bus.
At the third level the master requests a data transfer and
acknowledges the response of the slave.
The protocol involved in each of these levels is given below.

\subsubsection{Bus Aquisition Protocol}

\small\tt \begin{verbatim}Step  Controller Action            Master i Action

 1                                 Wait until BGRiL negated.
                                   Assert BRQiL.
                                   Assert CBRL.

 2    Wait until it is
      Master i's turn to
      control the bus and
      previous master j
      has negated BRQjL.
      Negate BGRjL.
      Assert BGRiL.

 3                                 Note Assertion of BGRiL.
                                   Negate CBRL.

 4                                 Perform one or more
                                   bus transactions according to
                                   the protocol below.

 5                                 Negate BRQiL.
                                   Repeat Bus acquisition protocol
                                   as required.
\end{verbatim}\rm  \normalsize 

\subsubsection{Bus Transaction Protocol}

\small\tt \begin{verbatim}Step    Master Action
 1      Wait until TACL negated.

 2      Assert ATML

 3      Perform one or more bus
        transfers according to
        the protocol below.

 4      Negate ATML

 5      If CBRL is asserted
        then release bus
        otherwise retain control of bus
        and perform further transactions
        as required.


\subsubsection{Bus Transfer Protocol}

\small\tt \begin{verbatim}Step  Current Master Action        Slaves and Controller Action

 1    Drive AD2L-AD31L, R/WL and CO0L-CO3L.
      If R/WL is asserted
      then drive DA00L-DA37L as
         specified by CO0L-CO3L.

2     Assert TRQL.

3                             Note TRQL asserted. Wait 25ns.

4                             Decode AD2L-AD31L to see if selected.
                              If selected
                              then proceed
                              otherwise wait until TRQL negated.
                              If operation cannot be performed
                                 successfully,
                              then assert ERRL,
                              otherwise if R/WL is asserted
                                 then accept data on DA00L-DA37L as
                                    specified by CO0L-CO3L.
                                 otherwise present data on
                                    DA00L-DA37L as specified by CO0L-CO3L.

5                             Assert TACL.
                              If TACL not asserted by any slave
                                 within 2000ns of TRQL asserted
                              then the Controller asserts TACL and ERRL.

6     Note TACL asserted. Wait 25ns.

7     If ERRL asserted
      then note that transfer failed,
      otherwise If R/WL negated
         then accept data on DA00L-DA37L as
            specified by CO0L-CO3L.
      Remove AD2-AD31L, R/WL and CO0L-CO3L.
      If R/WL was asserted
      then remove DA00L-DA37L as specified
         by CO0L-CO3L.

8     Negate TRQL.
      If end of transaction
      then return to complete
         transaction protocol.
      otherwise continue.

9                             Note TRQL negated.

10                            Negate ERRL.
                              If R/WL was negated
                              then remove DA00L-DA37L.

11                            Negate TACL.

12    Wait until TACL negated.
      Repeat bus transfer protocol.
\end{verbatim}\rm  \normalsize 



\section{THE CONTROL PROCESSOR BOARD}

\subsection{Introduction}
The control processor board (CSD134) provides a fully-programmed system control
facility based on a Motorola MC68000 8 Mhz Clock rate
micro-processor. It has a system bus
interface that allows access to the complete address space of the system
(EUCSD) bus. It also has a local bus through which it may access 16k of
on board memory, an RS232 port and a programmable timer.
This bus is also taken off board to allow expansion of the local resources.
Full details of the MC68000 processor are contained in the Manufacturer's
manual [MC69000UM].


\subsection{Switches and indicators}
When viewed from the front, the layout of the control switches
and indicators on the control processor board is as follows:

\small\tt \begin{verbatim}   |
   |----
   |  [| MSD   Address Select Switches (4 Hex Digits).
   |----
   |  [|       These select the high order 16 address bits used to
   |----       access the control processors interrupt and
   |  [|       status registers within the system bus real
   |----       address space.
   |  [| LSD
   |----
   |            RS232 port baud rate select switch.
   |----        Positions  :
   |  [|        0:19200.0  4:  3600.0  8:  1200.0  C:  134.5
   |----        1: 9600.0  5:  2400.0  9:   600.0  D:  110.0
   |            2: 7200.0  6:  2000.0  A:   300.0  E:   75.0
   |            3: 4800.0  7:  1800.0  B:   150.0  F:   50.0
   |----
   | 0 |        Run indicator.
   | 0 |        User mode indicator.
   |----
   |----        System manual reset switch.
   | - |        Normally in UP position.
   |----        Depress switch and release to reset system.
   |            This switch is interlocked with the mains key
   |----        switch.  The system will not reset unless the
   |   |        mains key switch is in the reset enable
   |   |        position adjacent to the off position.
   |   |        (Regardless of how hard you press the system
   |   |        reset switch!)
   |   |
   |   |
   |   |
   |   |         Control processor local bus connector.
   |   |
   |   |
   |   |
   |   |
   |   |
   |----
   |
\end{verbatim}\rm  \normalsize 

\subsection{Control Processor Address Space}

The address outputs from the MC68000 on the control processor are used
to control access to the system bus, local bus and the on board memory
and I/O devices.
The 16MByte address space of the processor is split into regions.
Each region is associated with a group of devices each having a particular
set of properties.

The most significant address bit (A23) is used to distinguish between
access to local devices(A23=0) and the EUCSD system bus(A23=1). This
is the most important division and the two cases are dealt with separately.

\subsubsection{System Bus Address Mapping Registers}

There are 8 registers which supply the 12 high order address bits of the
system bus(AD31L-AD20L). These are indexed by address lines A22-A20 in
both the system bus and the local device regions of the MC68000 address
space.
They can only be written. Writes to these registers take place only in the
local device region.
Software should maintain shadow locations in RAM to record their contents.


\subsubsection{Local Devices}

When accessing the local region of the address space, A19 determines
whether the local bus or the address mapping registers are accessed.
When accessing the mapping registers, bits A22-A20 select which register
is written. Address bits A18-A1 are ignored. Only data bits 4-15 are
written to these registers. The individual bytes of the address registers
may be updated separately.

When accessing the local bus, A22 is used to determine the protocol
to be used.

\hspace*{0.3 in} Bits A18-A1 are used as the bus address lines.
\\ \hspace*{0.3 in} Bits A21-A20 are ignored.
\\ \hspace*{0.3 in} If A22=0 the MC68000 asynchronous handshake is used.

A one micro-second time-out is provided to ensure all transfers
complete. A M68000 bus error is generated on a local M68000 bus time-out.
If A22=1 a synchronous protocol that is compatible with Motorola
MC6800 family I/O devices is used. As A22 is used to gate the
appropriate control signals the local bus appears as two logically
distinct buses separated in time. They do, however, share both data
and address lines. The UDS and LDS control signals from the MC68000
are used to determine which bytes of the local bus are active.
Thus, they provide the least significant address line.

The on board memory and I/O devices are interfaced through these buses.
The buses are also taken off board to allow expansion of the local
address space. In particular the Ethernet local area communications
network station is connected through this local bus.

\subsubsection{Local Bus Pin Assignment}

The local bus is taken off board on a DIN41612 C 96/64 way connector.
This is positioned at the front of the board.

\small\tt \begin{verbatim} pin no         row    
           a            c    

      1    GND         GND    
      2    GND         GND    
      3    unused      unused    
      4    unused      unused    
      5    unused      A1    
      6    A2          A3    
      7    A4          A5    
      8    A6          A7    
      9    A8          A9    
      10    A10        A11    
      11    A12        A13    
      12    A14        A15    
      13    A16        A17    
      14    A18        ADACK'    
      15    CLK        E    
      16    AS'        DTACK'    
      17    UDS'       LDS'    
      18    IRQ7'      IRQ6'    
      19    VMA'       R/W'    
      20    RST'       LOCK'    
      21    IRQ5'      IRQ4'    
      22    unused     unused    
      23    D0         D1    
      24    D2         D3    
      25    D4         D5    
      26    D6         D7    
      27    D8         D9    
      28    D10        D11    
      29    D12        D13    
      30    D14        D15    
      31    unused     unused    
      32    unused     unused    
\end{verbatim}\rm  \normalsize 

\subsubsection{Local Bus Signal Description}

\small\tt \begin{verbatim} signal     input    description
            output

 A1-A18       O      MC68000 address lines A1-A18

 D0-D15       I/O    MC68000 data lines D0-D15

 AS'          O      MC68000 address strobe.
                     Active only when M68000 bus in operation.

 UDS',LDS'    O      MC68000 Data strobes.
                     Active only when M68000 bus in operation.

 R/W'         O      MC68000 read/write line.

 VMA'         O      MC68000 valid memory address line.
                     Active only when M6800 bus in operation.

 CLK          O      MC68000 8 MHz clock.

 E            O      MC68000 800KHz Enable clock.

 RST'         O      MC68000 reset. Low during power-up,
                     manual and software resets.

 DTACK'       I      MC68000 data transfer acknoledge.

 ADACK'       I      Address acknowledge. A TTL low on
                     this line suppresses the local bus
                     time-out. Used to enable slow response
                     from slaves.

 IRQ4',IRQ5', I      Interrupt request lines. TTL low signals
 IRQ6',IRQ7'         on these lines cause an auto-vectored
                     interrupt at the corresponding priority
                     level. IRQ7' is a non maskable interrupt.

 LOCK'        I      System bus lock. A TTL low on this
                     line will cause the control processor
                     to gain and retain control of the
                     system bus. For use by diagnostic
                     hardware.
\end{verbatim}\rm  \normalsize 
\subsubsection{Local Bus Timing}
The timing of the signals is generally the same as an 8MHz MC68000.
However, the bus is buffered and delays of approximately 20ns should
be taken into account when analysing timing requirements.

ADACK' has similar timing characteristics to DTACK', and must be
asserted within 800ns of AS' being asserted in order to suppress
the local bus time-out.

LOCK' is synchronised internally and there are few constraints
on its timing.


\subsubsection{System Bus}

When A23=1 the system EUCSD bus is accessed. Address lines A22-A20
determine which address mapping register is used to provide the high
order 12 bits of the system bus address(AD31L-AD20L). Address lines
A19-A2 form the low order 18 bits of the address.

A1 is used to determine which pair of bytes is accessed on the system
bus. When A1=0 bytes DA0XL and DA1XL are active.
When A1=1 byte DA2XL and DA3XL are active.
Note that it is not possible to access bytes within both of these pairs
simultanteously. UDS and LDS are used to determine which bytes within
the pairs are accessed. UDS controls DA0XL and DA2XL while LDS controls
DA1XL and DA3XL. Thus to the MC68000 byte DA0XL has an address with two
least significant bits on 0, DA1XL is accessed with low order address
of 1 and so on.


\subsubsection{Control Processor Address Space Summary}

\small\tt \begin{verbatim}A23 A22 A21 A20 A19 A18-A2 A1 (A0)
 0 | 0 |---?---| 0 |----A----| 0  M68000 local space A high byte
 0 | 0 |---?---| 0 |----A----| 1  M68000 local space A low byte
 0 | 1 |---?---| 0 |----A----| 0  M6800 local space A high byte
 0 | 1 |---?---! 0 |----A----| 1  M6800 local space A low byte
 0 |-----M-----| 1 |----?----| 0  Map reg M high byte(write only)
 0 |-----M-----| 1 |----?----| 1  Map reg M  low byte(write only)
 1 |-----M-----|-----A----| 0  0  System bus (map reg M)A  DAX0L
 1 |-----M-----|-----A----| 0  1  System bus (map reg M)A  DAX1L
 1 |-----M-----|-----A----| 1  0  System bus (map reg M)A  DAX2L
 1 |-----M-----|-----A----| 1  1  System bus (map reg M)A  DAX3L
\end{verbatim}\rm  \normalsize 


\subsection{On board Facilities}

The control processor board contains some memory and a number of
I/O devices.
These appear in the local address space of the MC68000 control processor.

\subsubsection{Memory}

The on board memory consists of 16K bytes organised as 8K of 16 bit words.
It is link selectable as EPROM(2716) or RAM in 4K byte blocks. This
occupies locations 00000-04000 of the local M68000 bus.
Normally the first block is bootstrap EPROM and the remainder is RAM.


\subsubsection{I/O Devices}

The on board I/O devices consist of a RS232 port, a programmable counter
timer and a mains key switch position sense register. They are located
at addresses 00000-001FF of the local M6800 bus.

\subsubsection{The Key Switch Register}

Located at address 00031 of the local M6800 bus this is a simple read
only register.
The 4 low-order bits of this byte reflect the position of the
mains switch. The coding is as follows:

\small\tt \begin{verbatim}       Switch Position                             Code
            0 (furthest anti-clockwise)          Power off.
            1 (Manual reset enable)                  0
            2                                        1
            3                                        2
            4                                        4
            5 (furthest clockwise)                   8
\end{verbatim}\rm  \normalsize 
Bits 4-7 of the bus are not driven when this register is read. These bits
may contain unpredictable data. Care should be taken to mask off these
bits when using the contents of the register.


\subsubsection{The RS232 Port}

This is a Motorola MC6850 ACIA. For programming details see the appropriate
data sheet.
It appears as two low order byte locations within the M6800 bus.
Both have a different meaning depending on whether it is being read or written.
The command (write-only) and status (read-only) register is at 000C1.
The data registers are at location 000C3.
The ACIA interrupt output is connected to interrupt level 5 of the local
bus and hence uses auto-vector 5 (longword at address 000074 of the local
M68000 bus).
Both the transmit and receive data rates are determined by the setting
of a single hex coded switch visible at the front of the board.
For details of their coding refer to the section on switches and indicators.


\subsubsection{The Programmable Timer}

This is a Motorola MC6840 PTM. For programming details see the appropriate
data sheet.
It appears as 8 high order byte locations within the M6800 bus.
As with the ACIA,
each register has a different meaning depending on whether it is being read
or written.
Their addresses within the M6800 address space are as follows:

\small\tt \begin{verbatim}Address    Read              Write

00100  Undefined            Control Register 1 or 3
00102  Interrupt Status     Control Register 2
00104  Counter 1 high byte  Constant Register 1 high byte
00106  Counter 1  low byte  Constant Register 1  low byte
00108  Counter 2 high byte  Constant Register 2 high byte
0010A  Counter 2  low byte  Constant Register 2  low byte
0010C  Counter 3 high byte  Constant Register 3 high byte
0010E  Counter 3  low byte  Constant Register 3  low byte
\end{verbatim}\rm  \normalsize 
The PTM interrupt is connected to interrupt level 6 of the local bus and
hence uses auto-vector 6 (longword at address 000078 of the local M68000 bus).
The internal clock oscillates at 800KHz.

\hspace*{0.3 in} Counter input 1 is derived from the system bus 100Hz mains clock.
\\ \hspace*{0.3 in} Counter input 2 is derived from counter 3's output.
\\ \hspace*{0.3 in} Counter input 3 is derived from counter 1's output.

This allows cascading of the counter channels.
The gate inputs to all channels are permanently enabled.




\subsection{Control Processor Addresss Space Index}

This is a complete guide to the devices within the M68000 address space.

\small\tt \begin{verbatim}    Addresses             Device
 000000---000FFF  Local bootstrap EPROM
 001000---003FFF  Local RAM (switchable to EPROM)
 004000---07FFFB  Unused
                  (available for local M68000 bus expansion)
 07FFFC---07FFFF  Ethernet Station Interface (if fitted)
 080000---0FFFFF  Address map register 0
 100000---17FFFF  Same as 000000-7FFFFF
 180000---1FFFFF  Address map register 1
 200000---27FFFF  Same as 000000-7FFFFF
 280000---2FFFFF  Address map register 2
 300000---37FFFF  Same as 000000-7FFFFF
 380000---3FFFFF  Address map register 3
 400000---400030  Unused
 400030(2)40003E  Unused
 400031(2)40003F  Mains switch register (low byte)
 400040---4000BF  Unsafe to access
 4000C0(2)4000CE  Unused
 4000C1(2)4000CF  ACIA (low bytes)
 4000D0---4000FF  Unsafe to access
 400100(2)40010E  PTM  (high bytes)
 400101(2)40010F  Unused
 400110---4001FF  Unsafe to access
 400200---47FFFF  Unused
                  (available for local M6800 bus expainsion)
 480000---4FFFFF  Address map register 4
 500000---57FFFF  Same as 400000-47FFFF
 580000---5FFFFF  address map register 5
 600000---67FFFF  Same as 400000-47FFFF
 680000---6FFFFF  Address map register 6
 700000---77FFFF  Same as 400000-47FFFF
 780000---7FFFFF  Address map register 7
 800000---8FFFFF  System Bus RRR00000-RRRFFFFF, RRR = Map Reg 0
 900000---9FFFFF  System Bus RRR00000-RRRFFFFF, RRR = Map Reg 1
 A00000---AFFFFF  System Bus RRR00000-RRRFFFFF, RRR = Map Reg 2
 B00000---BFFFFF  System Bus RRR00000-RRRFFFFF, RRR = Map Reg 3
 C00000---CFFFFF  System Bus RRR00000-RRRFFFFF, RRR = Map Reg 4
 D00000---DFFFFF  System Bus RRR00000-RRRFFFFF, RRR = Map Reg 5
 E00000---EFFFFF  System Bus RRR00000-RRRFFFFF, RRR = Map Reg 6
 F00000---FFFFFF  System Bus RRR00000-RRRFFFFF, RRR = Map Reg 7
\end{verbatim}\rm  \normalsize 

\subsection{System Bus Control and Status Registers}
The control processor provides a number of registers that can be accessed
as slave devices from the system EUCSD bus.
These enable the processor to be interrupted by any master on the system
bus.
They also provide information about the current state of the control
processor.

The locations they occupy within the system bus address space are determined
by 4 hex coded switches that are visible from the front of the board.
These specify the high order address bits (AD16L-AD31L) used to access the
registers.

The registers are 16 bits wide and connected to bytes DA2XL and DA3XL of
the system bus.
Bytes DA0XL and DA1XL are unconnected and access to these
bytes alone does not cause the slave logic to acknowledge an access.
The two bytes are individually accessible. The DA2XL byte is common to
each of the registers and is read only. The 8 distinct DA3XL bytes are
selected by address lines AD15L-AD13L.
Note that this allows fairly coarse segmentation to provide controlled
access to the individual registers.
At present the status bits are active high, but may be made active
low by a trivial hardware modification.

\subsubsection{Control and Status Register Address Map}
To summarise the registers appear in the system address space as follows:

\small\tt \begin{verbatim}  DA2XL byte

    SSSS0002(4)SSSSFFFE  Combined interrupt state register
                         (read only)

  DA3XL bytes

    SSSS0003(4)SSSS1FFF  Processor State register
                         (read only)
    SSSS2003(4)SSSS3FFF  Level 1 interrupt register
    SSSS4003(4)SSSS5FFF  Level 2 interrupt register
    SSSS6003(4)SSSS7FFF  Level 3 interrupt register
    SSSS8003(4)SSSS9FFF  Level 4 interrupt register
    SSSSA003(4)SSSSBFFF  Level 5 interrupt register
    SSSSC003(4)SSSSDFFF  Level 6 interrupt register
    SSSSE003(4)SSSSFFFF  Level 7 interrupt Register

    (SSSS is the setting if the address select switches)
\end{verbatim}\rm  \normalsize 
Note that the binary encoding of bits AD15L-AD13L give the level of the
interrupt register.


\subsubsection{Register Bit Encodings$>$}
The meaning of each of the register bits when read are as follows:

\subsubsection{Combined Interrupt State Register}
\small\tt \begin{verbatim}    bit
     7    Priority level 7 interrupt pending
     6    Priority level 6 interrupt pending
     5    Priority level 5 interrupt pending
     4    Priority level 4 interrupt pending
     3    Priority level 3 interrupt pending
     2    Priority level 2 interrupt pending
     1    Priority level 1 interrupt pending
     0    Always 0
\end{verbatim}\rm  \normalsize 

\subsubsection{Processor State Register}
\small\tt \begin{verbatim}    bit
     7    Function code FC2 for last cycle
     6    Function code FC1 for last cycle
     5    Function code FC0 for last cycle
     4    Always 0
     3    Processor halted after fatal bus error.
     2    Always 0
     1    Always 1
     0    Always 1
\end{verbatim}\rm  \normalsize 

\subsubsection{Interrupt Registers}
\small\tt \begin{verbatim}    bit
     7    Interrupt pending at corresponding level
    0-6   Always 0
\end{verbatim}\rm  \normalsize 


\subsubsection{Requesting Interrupts}
When any data is written to an interrupt register the data is discarded
and an interrupt at the corresponding M68000 priority level is requested.
At the same time Bit 7 of the interrupt register is set, together with
the corresponding bit in the combined interrupt state register.
Once the processor has acknowledged an interrupt at that level the interrupt
request is removed. At the same time bit 7 of the interrupt register
is cleared, together with the corresponding bit in the combined interrupt
state register. During the interrupt acknowledge the processor is
forced into the auto-vector mode of operation.

Note that care must be taken to ensure that system bus interrupts are not
lost.
In general, this will require that details of the interrupt request are
stored in shared system memory. These details can then be examined
by interrupt handling software on the control processor.
This is particularly true for interrupt levels 4-7 which may also be
generated by I/O devices attached to the control processor's local
bus.
The situation requires even more care when there is more than one source
of interrupts from the system bus.
Steps must be taken to ensure mutual exclusion on the interrupt information
held in shared memory.
This might consist of a semaphore that is locked prior to storing the
interrupt details and before issuing the interrupt request.
The semaphore is subsequently released by the control processor on
completion of the interrupt service routine.



\section{LEVEL 1 GRAPHICS SYSTEM}

\subsection{Introduction}
The level 1 graphics board (CSD154) is a simple, write only, colour
raster graphics controller and frame store.
It provides a display of up to 1024*1024 pixels of four bits each.
It can be configured to drive a large variety of monitors, both
interlaced and non-interlaced and at different data, line and frame rates.
It generates 3 TTL video outputs allowing 8 different colours
to be displayed.

A further board (CSD155) can be added to give an additional four bits per
pixel and a colour map suitable for driving analogue input colour
monitors.
Together they can display up to 256 different colours at one time.
These colours can be selected from a total of 32768 shades.


\subsection{Switches and indicators}
When viewed from the front of the system the layout of the control switches
and indicators on the control processor board is as follows:

\small\tt \begin{verbatim}   |
   |----
   |  [| MSD   Address Select Switches (4 Hex Digits).
   |----
   |  [|       Selects the high order 14 address bits used to
   |----       access the frame store and its associated control
   |  [|       registers within the system bus real address
   |----       space. The board is disabled if the LSD switch
   |  [| LSD   is not a multiple of 4.
   |----
   |
   |
   |
   |
   |
   |
   |----
   | 0 |        Access indicator. On if a framestore update
   |----                          is in progress
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
   |
\end{verbatim}\rm  \normalsize 

\subsection{Coordinate System}
The frame store is an array of 1024*1024 pixels.
Pixel (0,0) is at the bottom left of the array and pixel (1023,1023) is
at the top right of the array.
The attached monitor will display a rectangular sub-region of this array.
The size of the displayed area is determined by the Monitor specifications
and is configured by PROM's on the graphics board.
The display area for the Mitsubishi C3419E monitors is 512(V)*688(H) pixels.
The origin of the displayed region is determined by the contents of
a write only register, the START OF DISPLAY REGISTER.
The Start of Display register is a 16 bit register.
The 10 most significant bits specify the Y index of the TOPMOST
displayed pixel.
The 6 least significant bits specify the X index of the LEFTMOST displayed
pixel, DIVIDED by 16. The X index of the first displayed pixel must be
a multiple of 16. The two bytes of the register may be written separately.
If the origin is such that an overflow occurs then the displayed region
wraps around from high to low index pixels.


\small\tt \begin{verbatim} (0,1023)                                                      (1023,1023)
   ------------------------------------------------------------------
   |                                                                |
   |              Frame Store                                       |
   |                                                                |
   |                                                                |
   |       ------------------------------------------<- Y Start of  |
   |       |                               ^        |     Display   |
   |       |                               |        |               |
   |       |      Displayed Area           |        |               |
   |       |      (Mitsubishi C3419E)      |        |               |
   |       |                               |        |               |
   |       |                               |        |               |
   |       |                               |        |               |
   |       |<--------------------- 688 ----+------->|               |
   |       |                               |        |               |
   |       |                               |        |               |
   |       |                              512       |               |
   |       |                               |        |               |
   |       |                               |        |               |
   |       |                               v        |               |
   |       ------------------------------------------               |
   |       ^                                                        |
   |       |                                                        |
   |   X Start of Display                                           |
   |                                                                |
   |                                                                |
   ------------------------------------------------------------------
 (0,0)                                                         (1023,0)
\end{verbatim}\rm  \normalsize 


\subsection{System Bus Interface}
The level 1 graphics board provides a number of write only locations that
can be accessed as slave devices from the system EUCSD bus.

The locations they occupy within the system bus address space are determined
by 4 hex coded switches that are visible from the front of the board.
These specify the 14 high order address bits (AD31L-AD18L) used to access
the frame store and control registers.
The next highest address line AD17L determines whether the frame store
(AD17L is 0) or the control registers (AD17L is 1) are are accessed.

If the control registers are accessed AD16L is used to determine
whether the general control registers (AD16L is 0) or the colour map
(AD16L is 1) is accessed. Note that accessing the colour map is effective
only when the CSD155 board is availble.


\subsection{Frame Store Addressing}
The Frame Store appears as a linear sequence of 128K bytes in the system bus
address space. This may be considered as a 1024*1024 array of bits, organised
as groups of 8 bits in a 1024*128 array of bytes. Increasing byte addresses
correspond to increasing X coordinates first and increasing Y coordinates
second. Within a byte the most significant bit corresponds to the pixel
with lowest X coordinate. Thus, if we consider a particular sequence of
pixels as a binary number they appear on the display in the 'natural'
left to right order of decreasing significance.

Up to 4 aligned bytes may be written in a single frame store access.
The user should note that internally 16 bit operations are performed.
This implies that the store cycle time is doubled for 32 bit accesses.


\subsection{Pixels - CSD154 board only}
Each pixel is associated with 4 bits of data. Each bit is stored
in a separate 1024*1024 bit storage array or PLANE.
The contents of planes 0, 1 and 2 determine whether the red, green and
blue guns of the monitor are on or off. Plane 3 , the 'cursor' plane
allows the sense of data from planes 0, 1, and 2 to be inverted.

Thus, for any given pixel:

\small\tt \begin{verbatim}    if plane 3 = 0
          red gun is on if plane 0 = 1
        green gun is on if plane 1 = 1
         blue gun is on if plane 2 = 1

    if plane 3 = 1
          red gun is off if plane 0 = 1
        green gun is off if plane 1 = 1
         blue gun is off if plane 2 = 1
\end{verbatim}\rm  \normalsize 
Note that a pixel may be any one of the following colours :

\small\tt \begin{verbatim}    black      all off        0000 or 1111
    red        red only       0001 or 1110
    green      green only     0010 or 1101
    yellow     red+green      0011 or 1100
    blue       blue only      0100 or 1011
    magenta    red+blue       0101 or 1010
    cyan       green+blue     0110 or 1001
    white      red+green+blue 0111 or 1000
\end{verbatim}\rm  \normalsize 

Notice that the colour displayed when plane 3 is 0 is the complement
of that displayed when plane 3 is 1, provided that planes 0, 1 and 2
remain the same. Thus plane 3 may be used as a cursor plane on which
any symbol written will probably be noticable, regardless of the contents
of the other planes.


\subsection{Pixels - CSD154 and CSD155 two board system}

With the CSD155 option installed each pixel is associated with 8 bits
of data. Each bit is again stored in a separate 1024*1024 colour plane.
The method of updating the frame store is unchanged.
However, the manner in which each pixel is displayed is altered.

When a pixel is displayed the 8 bits of data are used as an index to
a writable COLOUR MAP. For each of the 256 possible values a pixel
may take a 16 bit value is generated by the colour map.
These 16 bit values are written into the colour map before the
desired picture can be displayed.
The 16 bits are used as three 5 bit fields and a single 1 bit field.
The 5 bit fields are used as an unsigned integer to determine the
analogue intensity of the red, green and blue guns of the CRT display.
The 1 bit field is used as a control bit that determines whether the
pixel flashes at one 16th of the display field rate; about 3 times a second.

The colour map may be updated by normal writes to the graphics system.
The low order address lines (AD9L-AD2L) are used to index the colour map
and the data written provides the 16 bit values generated by the colour map.
The colour map appears to the bus as 32 bit entries, the 16 high order
bits being ignored. The individual bytes of the colour map entries may
be written separately.

The operation of writing a single new entry
to the colour map will cause the display to be blanked for 3 pixels.
This is to minimise the effect of generating incorrect data when a change
is made.
It may be possible to use the vertical sync output from the controller
to synchronise colour map changes to the display vertical blanking period.
This would allow colour map updates to go completely unnoticed on the display.


\subsection{Updating the Frame Store}
Only write accesses to the frame store are allowed.
When the frame store is written an UPDATE OPERATION takes place.
The data when written does not go directly to the planes, but is used
as a mask. Each bit in the mask corresponds to a pixel as discussed in
the section on frame store addressing. If a data bit in the mask is 0
then no change is made to the corresponding pixel. If a bit is 1 then the
pixel is updated. The change made to the bits that make up the pixel is
determined by the contents of two control registers.

The PLANE ENABLE REGISTER is a single byte and contains a bit corresponding
to each of the colour planes.
If the bit for a plane is zero, then that plane is not changed by frame store
update operations. If the bit is 1 then the plane may be modified by the
update operation.
If the CSD154 board is used alone then only the 4 least significant
bits are used.

The COLOUR REGISTER is a single byte and contains a bit corresponding
to each of the colour planes.
When a frame store update operation takes place the contents of the colour
register is written to the corresponding plane of each pixel that has 1
in the data mask.
This is of course conditional on the enable bit for that plane being 1.
If the CSD154 board is used alone then only the 4 least significant
bits are used.

This arrangement allows all planes to be updated simultaneously. However,
it does not have any overall speed up when drawing finely detailed pictures.
For example, to clear the frame store the following must be performed.
First all 1's are written to the plane enable register.
Then all 0's are written to the colour register.
Finally all 1's are written to all the frame store locations.

To draw an arbitrarily coloured picture we must proceed as follows.
For each colour the colour register must be written
before writing 1's to each pixel that will be that colour in the final
picture. This must be repeated until the detail for all colours is drawn.

For 'layered' applications such as VLSI plots it is sufficient to proceed
as follows.
First write all 1's to the colour register.
Then for each layer write a single 1 to the plane enable register, before
updating the frame store with the detail for that layer. Agian this must
be repeated until the detail for all of the layers is drawn.


\subsection{Register Address Map}
To summarise, the registers appear in the system address space as follows:


\small\tt \begin{verbatim}    SSST00000 - SSST0FFFF  Frame store.

    SSST20000(4)SSST2FFFC  Plane enable register.
    SSST20001(4)SSST2FFFD  Colour register.
    SSST20002(4)SSST2FFFE  Start of Display register.

    SSST30002(4)SSST3FFFE  Colour map registers.

    SSST is the setting of the board address select switches
    The system is deselected unless T is a multiple of 4.
\end{verbatim}\rm  \normalsize 

\subsection{Register Bit Encodings}

Collectively the general control registers may be considered as
a single 32 bit word. Each of the bytes may be accessed separately.
The meaning of each of the bits in order of decreasing
significance is as follows:

Byte 0 (MSByte) - Plane Enable register

\small\tt \begin{verbatim}     bit 7 (MSB) - Plane 7 enable bit -
     bit 6       - Plane 6 enable bit  | Significant only
     bit 5       - Plane 5 enable bit  | with CSD155 extension.
     bit 4       - Plane 4 enable bit -
     bit 3       - Plane 3 enable bit
     bit 2       - Plane 2 enable bit
     bit 1       - Plane 1 enable bit
     bit 0 (LSB) - Plane 0 enable bit
\end{verbatim}\rm  \normalsize 
\hspace*{0.3 in} If a bit is 0, updates to corresponding plane are disabled
\\ \hspace*{0.3 in} If a bit is 1, updates to corresponding plane are enabled

Byte 1 - Colour Register

\small\tt \begin{verbatim}     bit 7 (MSB) - Plane 7 data bit -
     bit 6       - Plane 6 data bit  | Significant only
     bit 5       - Plane 5 data bit  | with CSD155 extension.
     bit 4       - Plane 4 data bit -
     bit 3       - Plane 3 data bit
     bit 2       - Plane 2 data bit
     bit 1       - Plane 1 data bit
     bit 0 (LSB) - Plane 0 data bit
\end{verbatim}\rm  \normalsize 
\hspace*{0.3 in} The content of each bit is written to the corresponding
\\ \hspace*{0.3 in} plane during a suitably enabled and masked update operation.

Bytes 2 and 3 (LSByte) - Start of Display Register.

\small\tt \begin{verbatim}     byte 2 bits 7-0
     byte 3 bits 6&7 - Y Finishing Index
                       Y index of the last pixel displayed.
                       byte 2 bit 7 is the most significant bit.
                       byte 3 bit 6 is the least significant bit.

     byte 3 bits 5-0 - X Starting Index
                       X Index/16 of first pixel displayed.
                       The X index of the first pixel displayed
                       is always a multiple of 16.
                       bit 5 is the most significant bit.
\end{verbatim}\rm  \normalsize 

The colour map entries are 16 bits wide, but are 32 bit aligned.
Only the Least significant 16 bits are used. Either of the two bytes
may be written separately.

They have the following form :

\small\tt \begin{verbatim}     byte 2 bit 7    - Flash bit
                       If 0 pixel is steady
                       If 1 pixel alternates between colour specified
                       by rest of entry and black every 16 fields
                       (about 3 times a second)

     byte 2 bits 6-2 - Blue intensity
                       byte 2 bit 6 is the most significant bit.

     byte 2 bits 1 & 0,
     byte 3 bits 7-5 - Green intensity
                       byte 2 bit 1 is the most significant bit.

     byte 3 bits 4-0 - red intensity
                       byte 3 bit 4 is the most significant bit.
\end{verbatim}\rm  \normalsize 

\subsection{Software Support Routines}
A number of standard routines are available for using the Level 1 Graphics
System.
The folloing routines are written in assembler and their close interaction
with the hardware exploits the full potential of the graphics system.
their peformance is such that they should be used whenever possible.
In assembler, parameters are passed in registers d0, d1, ... d5 in the
order specified by the prototypes given below.

plot(x, y)

Sets the pixel at coordinate (x, y) to the current
contents of the colour register. The planes affected
are those specified by the plane enable register.

fill(x0, y0, x1, y1)

Fills a rectangular area bounded by the coordinates
(x0, y0) and (x1, y1). The colour used and planes
affected are taken to be the current contents of
the colour and plane enable registers.
If x0$>$x1 or y0$>$y1 the the area filled is wrapped
around the frame store.

line(x0, y0, x1, y1)

Draws a line between the coordinates (x0, y0) and
(x1, y1). The colour used and planes affected are
taken to be the current contents of the colour and
plane enable registers.

triangle(x0, y0, x1, y1, x2, y2)

Draws a filled triangle with vertices (x0, y0),
(x1, y1) and (x2, y2). The colour used and planes
affected are taken to be the current contents of
the colour and plane enable registers.

trapeze(x0l, x0r, y0, x1l, x1r, y1)

Draws a filled trapezium with parallel sides
parallel to the X axis. The coordinates of the
vertices are (x0l, y0), (x0r, y0), (x1l, y1) and
(x1r, y1). The colour used and plane affected are
taken to be the current contents of the colour
and plane enable registers.
Trapeze is primarily intended for polygon filling.

In other languages further routines may be provided. This will be in
addition to suitably interfaced calls to the basic routines given above.


\section{M68000 Virtual Memory Daughter Board}

\subsection{Introduction}
The M68000 virtual memory daughter board (CSD161) is a small board
which can be used in place of any M68000 or M68010 64 pin DIL chip.
It provides the address translation hardware necessary to support
virtual memory.
When viewed from the rest of the system, the board appears as a standard
M68000 chip with slighty modified timing between access cycles.

The translation hardware consists of one or two M68451 memory management
units (MMU's).
The MMU's may be located at any address within the physical address space
of the system.
The address of each MMU is independently determined by a single PAL chip.
On the APM boot processor board this is currently HEX 100000 and HEX 100040.
Access to the MMU registers is hidden from the rest of the system.
Similarly, translation faults and vectored interrupts from the MMU are
not apparent off board.


\vspace{.75in} view:apm.mss printed on 16/02/89 at 23.00

\newpage
\tableofcontents
\end{document}
